Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MicroMipsInstrFPU.td @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
35 def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, 35 def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
36 CEQS_FM_MM<0>; 36 CEQS_FM_MM<0>;
37 def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, 37 def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
38 CEQS_FM_MM<1>; 38 CEQS_FM_MM<1>;
39 39
40 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, IIBranch, MIPS_BRANCH_F>, 40 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
41 BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; 41 BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
42 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, IIBranch, MIPS_BRANCH_T>, 42 def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
43 BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6; 43 BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
44
45 def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
46 ROUND_W_FM_MM<0, 0x6c>;
47 def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 44 def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
48 ROUND_W_FM_MM<0, 0x24>; 45 ROUND_W_FM_MM<0, 0x24>;
49 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
50 ROUND_W_FM_MM<0, 0x2c>;
51 def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 46 def ROUND_W_S_MM : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
52 ROUND_W_FM_MM<0, 0xec>; 47 ROUND_W_FM_MM<0, 0xec>;
53 def TRUNC_W_S_MM : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
54 ROUND_W_FM_MM<0, 0xac>;
55 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
56 fsqrt>, ROUND_W_FM_MM<0, 0x28>;
57 48
58 def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, 49 def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
59 ROUND_W_FM_MM<1, 0x6c>; 50 ROUND_W_FM_MM<1, 0x6c>;
60 def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 51 def CVT_W_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
61 ROUND_W_FM_MM<1, 0x24>; 52 ROUND_W_FM_MM<1, 0x24>;
93 ABS_FM_MM<1, 0xd>; 84 ABS_FM_MM<1, 0xd>;
94 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>, 85 def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>,
95 ABS_FM_MM<1, 0x2d>; 86 ABS_FM_MM<1, 0x2d>;
96 87
97 def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 88 def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
98 ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>; 89 ABS_FM_MM<1, 0x1>, FGR_32;
99 90
100 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, 91 def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
101 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>; 92 II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
102 def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, 93 def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
103 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>; 94 II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>;
122 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, 113 def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
123 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; 114 II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
124 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, 115 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
125 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; 116 II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
126 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 117 def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
127 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 118 MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32;
128 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 119 def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
129 MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 120 MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32;
130 121
131 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 122 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
132 MADDS_FM_MM<0x1>; 123 MADDS_FM_MM<0x1>;
133 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 124 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
134 MADDS_FM_MM<0x21>; 125 MADDS_FM_MM<0x21>;
144 def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 135 def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
145 MADDS_FM_MM<0xa>; 136 MADDS_FM_MM<0xa>;
146 def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 137 def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
147 MADDS_FM_MM<0x2a>; 138 MADDS_FM_MM<0x2a>;
148 } 139 }
140
141 let AdditionalPredicates = [InMicroMips] in {
142 def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
143 II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>;
144 def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
145 FGR32Opnd, II_TRUNC>, ROUND_W_FM_MM<0, 0xac>;
146 def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
147 ROUND_W_FM_MM<0, 0x6c>;
148 def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
149 fsqrt>, ROUND_W_FM_MM<0, 0x28>;
150 }