CbC/CbC_llvm: lib/Target/Mips/MipsISelLowering.cpp comparison

comparison lib/Target/Mips/MipsISelLowering.cpp @ 95:afa8332a0e37 LLVM3.8

LLVM 3.8

author	Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date	Tue, 13 Oct 2015 17:48:58 +0900
parents	60c9769439b8
children	7d135dc70f03

comparison

equal deleted inserted replaced

-:f3e34b893a5f
+:afa8332a0e37
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/GlobalVariable.h"
 static cl::opt<bool>
 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
 cl::desc("MIPS: Don't trap on integer division by zero."),
 cl::init(false));
-cl::opt<bool>
-EnableMipsFastISel("mips-fast-isel", cl::Hidden,
-cl::desc("Allow mips-fast-isel to be used"),
-cl::init(false));
 static const MCPhysReg Mips64DPRegs[8] = {
 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
 };
 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
 N->getOffset(), Flag);
 }
 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
-switch (Opcode) {
+switch ((MipsISD::NodeType)Opcode) {
+case MipsISD::FIRST_NUMBER:      break;
 case MipsISD::JmpLink:           return "MipsISD::JmpLink";
 case MipsISD::TailCall:          return "MipsISD::TailCall";
 case MipsISD::Hi:                return "MipsISD::Hi";
 case MipsISD::Lo:                return "MipsISD::Lo";
 case MipsISD::GPRel:             return "MipsISD::GPRel";
 case MipsISD::DivRem16:          return "MipsISD::DivRem16";
 case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
 case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
 case MipsISD::Wrapper:           return "MipsISD::Wrapper";
+case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
 case MipsISD::Sync:              return "MipsISD::Sync";
 case MipsISD::Ext:               return "MipsISD::Ext";
 case MipsISD::Ins:               return "MipsISD::Ins";
 case MipsISD::LWL:               return "MipsISD::LWL";
 case MipsISD::LWR:               return "MipsISD::LWR";
 case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
 case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
 case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
 case MipsISD::SHILO:             return "MipsISD::SHILO";
 case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
+case MipsISD::MULSAQ_S_W_PH:     return "MipsISD::MULSAQ_S_W_PH";
+case MipsISD::MAQ_S_W_PHL:       return "MipsISD::MAQ_S_W_PHL";
+case MipsISD::MAQ_S_W_PHR:       return "MipsISD::MAQ_S_W_PHR";
+case MipsISD::MAQ_SA_W_PHL:      return "MipsISD::MAQ_SA_W_PHL";
+case MipsISD::MAQ_SA_W_PHR:      return "MipsISD::MAQ_SA_W_PHR";
+case MipsISD::DPAU_H_QBL:        return "MipsISD::DPAU_H_QBL";
+case MipsISD::DPAU_H_QBR:        return "MipsISD::DPAU_H_QBR";
+case MipsISD::DPSU_H_QBL:        return "MipsISD::DPSU_H_QBL";
+case MipsISD::DPSU_H_QBR:        return "MipsISD::DPSU_H_QBR";
+case MipsISD::DPAQ_S_W_PH:       return "MipsISD::DPAQ_S_W_PH";
+case MipsISD::DPSQ_S_W_PH:       return "MipsISD::DPSQ_S_W_PH";
+case MipsISD::DPAQ_SA_L_W:       return "MipsISD::DPAQ_SA_L_W";
+case MipsISD::DPSQ_SA_L_W:       return "MipsISD::DPSQ_SA_L_W";
+case MipsISD::DPA_W_PH:          return "MipsISD::DPA_W_PH";
+case MipsISD::DPS_W_PH:          return "MipsISD::DPS_W_PH";
+case MipsISD::DPAQX_S_W_PH:      return "MipsISD::DPAQX_S_W_PH";
+case MipsISD::DPAQX_SA_W_PH:     return "MipsISD::DPAQX_SA_W_PH";
+case MipsISD::DPAX_W_PH:         return "MipsISD::DPAX_W_PH";
+case MipsISD::DPSX_W_PH:         return "MipsISD::DPSX_W_PH";
+case MipsISD::DPSQX_S_W_PH:      return "MipsISD::DPSQX_S_W_PH";
+case MipsISD::DPSQX_SA_W_PH:     return "MipsISD::DPSQX_SA_W_PH";
+case MipsISD::MULSA_W_PH:        return "MipsISD::MULSA_W_PH";
 case MipsISD::MULT:              return "MipsISD::MULT";
 case MipsISD::MULTU:             return "MipsISD::MULTU";
 case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
 case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
 case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
 case MipsISD::ILVL:              return "MipsISD::ILVL";
 case MipsISD::ILVR:              return "MipsISD::ILVR";
 case MipsISD::PCKEV:             return "MipsISD::PCKEV";
 case MipsISD::PCKOD:             return "MipsISD::PCKOD";
 case MipsISD::INSVE:             return "MipsISD::INSVE";
-default:                         return nullptr;
+}
-}
+return nullptr;
 }
 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
 const MipsSubtarget &STI)
 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
 setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
 }
-// MIPS doesn't have extending float->double load/store
+// MIPS doesn't have extending float->double load/store.  Set LoadExtAction
-for (MVT VT : MVT::fp_valuetypes())
+// for f32, f16
+for (MVT VT : MVT::fp_valuetypes()) {
 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
+setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
+}
+// Set LoadExtAction for f16 vectors to Expand
+for (MVT VT : MVT::fp_vector_valuetypes()) {
+MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
+if (F16VT.isValid())
+setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
+}
+setTruncStoreAction(MVT::f32, MVT::f16, Expand);
+setTruncStoreAction(MVT::f64, MVT::f16, Expand);
 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
 // Used by legalize types to correctly generate the setcc result.
 // Without this, every float setcc comes with a AND/OR with the result,
 // we don't want this, since the fpcmp result goes to a flag register,
 setOperationAction(ISD::FMA,               MVT::f32,   Expand);
 setOperationAction(ISD::FMA,               MVT::f64,   Expand);
 setOperationAction(ISD::FREM,              MVT::f32,   Expand);
 setOperationAction(ISD::FREM,              MVT::f64,   Expand);
+// Lower f16 conversion operations into library calls
+setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
+setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
+setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
+setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
 setOperationAction(ISD::VASTART,           MVT::Other, Custom);
 setOperationAction(ISD::VAARG,             MVT::Other, Custom);
 setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
 // Create a fast isel object.
 FastISel *
 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
 const TargetLibraryInfo *libInfo) const {
-if (!EnableMipsFastISel)
+if (!funcInfo.MF->getTarget().Options.EnableFastISel)
 return TargetLowering::createFastISel(funcInfo, libInfo);
 return Mips::createFastISel(funcInfo, libInfo);
 }
-EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
+EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
+EVT VT) const {
 if (!VT.isVector())
 return MVT::i32;
 return VT.changeVectorElementTypeToInteger();
 }
 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
 // node if necessary.
 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
-DAG.getConstant(condCodeToFCC(CC), MVT::i32));
+DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
 }
 // Creates and returns a CMovFPT/F node.
 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
 SDValue False, SDLoc DL) {
 // Couldn't optimize.
 return SDValue();
 }
+static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
+TargetLowering::DAGCombinerInfo &DCI,
+const MipsSubtarget &Subtarget) {
+if (DCI.isBeforeLegalizeOps())
+return SDValue();
+SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
+ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
+if (!FalseC || FalseC->getZExtValue())
+return SDValue();
+// Since RHS (False) is 0, we swap the order of the True/False operands
+// (obviously also inverting the condition) so that we can
+// take advantage of conditional moves using the $0 register.
+// Example:
+//   return (a != 0) ? x : 0;
+//     load $reg, x
+//     movz $reg, $0, a
+unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
+MipsISD::CMovFP_T;
+SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
+return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
+ValueIfFalse, FCC, ValueIfTrue, Glue);
+}
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
 TargetLowering::DAGCombinerInfo &DCI,
 const MipsSubtarget &Subtarget) {
 // Pattern match EXT.
 //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
 // and Pos exceeds the word's size.
 EVT ValTy = N->getValueType(0);
 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
 return SDValue();
-return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
+SDLoc DL(N);
-ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
+return DAG.getNode(MipsISD::Ext, DL, ValTy,
-DAG.getConstant(SMSize, MVT::i32));
+ShiftRight.getOperand(0),
+DAG.getConstant(Pos, DL, MVT::i32),
+DAG.getConstant(SMSize, DL, MVT::i32));
 }
 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
 TargetLowering::DAGCombinerInfo &DCI,
 const MipsSubtarget &Subtarget) {
 // same.
 EVT ValTy = N->getValueType(0);
 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
 return SDValue();
-return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
+SDLoc DL(N);
-DAG.getConstant(SMPos0, MVT::i32),
+return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
-DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
+DAG.getConstant(SMPos0, DL, MVT::i32),
+DAG.getConstant(SMSize0, DL, MVT::i32),
+And0.getOperand(0));
 }
 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
 TargetLowering::DAGCombinerInfo &DCI,
 const MipsSubtarget &Subtarget) {
 case ISD::SDIVREM:
 case ISD::UDIVREM:
 return performDivRemCombine(N, DAG, DCI, Subtarget);
 case ISD::SELECT:
 return performSELECTCombine(N, DAG, DCI, Subtarget);
+case MipsISD::CMovFP_F:
+case MipsISD::CMovFP_T:
+return performCMovFPCombine(N, DAG, DCI, Subtarget);
 case ISD::AND:
 return performANDCombine(N, DAG, DCI, Subtarget);
 case ISD::OR:
 return performORCombine(N, DAG, DCI, Subtarget);
 case ISD::ADD:
 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
 SDValue Chain = Op.getOperand(0);
 SDValue Table = Op.getOperand(1);
 SDValue Index = Op.getOperand(2);
 SDLoc DL(Op);
-EVT PTy = getPointerTy();
+auto &TD = DAG.getDataLayout();
+EVT PTy = getPointerTy(TD);
 unsigned EntrySize =
-DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
+DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
-DAG.getConstant(EntrySize, PTy));
+DAG.getConstant(EntrySize, DL, PTy));
 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
-Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
+Addr =
-MachinePointerInfo::getJumpTable(), MemVT, false, false,
+DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
-false, 0);
+MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
+MemVT, false, false, false, 0);
 Chain = Addr.getValue(1);
 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) {
 // For PIC, the sequence is:
 // BRIND(load(Jumptable + index) + RelocBase)
 SDValue CCNode  = CondRes.getOperand(2);
 Mips::CondCode CC =
 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
-SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
+SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
 FCC0, Dest, CondRes);
 }
 SDValue MipsTargetLowering::
 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
 {
 SDLoc DL(Op);
 EVT Ty = Op.getOperand(0).getValueType();
-SDValue Cond = DAG.getNode(ISD::SETCC, DL,
+SDValue Cond =
-getSetCCResultType(*DAG.getContext(), Ty),
+DAG.getNode(ISD::SETCC, DL, getSetCCResultType(DAG.getDataLayout(),
-Op.getOperand(0), Op.getOperand(1),
+*DAG.getContext(), Ty),
-Op.getOperand(4));
+Op.getOperand(0), Op.getOperand(1), Op.getOperand(4));
 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
 Op.getOperand(3));
 }
 SDValue Cond = createFPCmp(DAG, Op);
 assert(Cond.getOpcode() == MipsISD::FPCmp &&
 "Floating point operand expected.");
-SDValue True  = DAG.getConstant(1, MVT::i32);
+SDLoc DL(Op);
-SDValue False = DAG.getConstant(0, MVT::i32);
+SDValue True  = DAG.getConstant(1, DL, MVT::i32);
+SDValue False = DAG.getConstant(0, DL, MVT::i32);
-return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
+return createCMovFP(DAG, Cond, True, False, DL);
 }
 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
 SelectionDAG &DAG) const {
 EVT Ty = Op.getValueType();
 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
 if (LargeGOT)
-return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16,
+return getAddrGlobalLargeGOT(
-MipsII::MO_GOT_LO16, DAG.getEntryNode(),
+N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
-MachinePointerInfo::getGOT());
+DAG.getEntryNode(),
+MachinePointerInfo::getGOT(DAG.getMachineFunction()));
-return getAddrGlobal(N, SDLoc(N), Ty, DAG,
-(ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP
+return getAddrGlobal(
-: MipsII::MO_GOT16,
+N, SDLoc(N), Ty, DAG,
-DAG.getEntryNode(), MachinePointerInfo::getGOT());
+(ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
+DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
 }
 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
 SelectionDAG &DAG) const {
 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
 // If the relocation model is PIC, use the General Dynamic TLS Model or
 // Local Dynamic TLS model, otherwise use the Initial Exec or
 // Local Exec TLS Model.
 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
+if (DAG.getTarget().Options.EmulatedTLS)
+return LowerToTLSEmulatedModel(GA, DAG);
 SDLoc DL(GA);
 const GlobalValue *GV = GA->getGlobal();
-EVT PtrVT = getPointerTy();
+EVT PtrVT = getPointerTy(DAG.getDataLayout());
 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
 // General Dynamic and Local Dynamic TLS Model.
 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
 const MipsTargetObjectFile *TLOF =
 static_cast<const MipsTargetObjectFile *>(
 getTargetMachine().getObjFileLowering());
-if (TLOF->IsConstantInSmallSection(N->getConstVal(), getTargetMachine()))
+if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
+getTargetMachine()))
 // %gp_rel relocation
 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
 }
 MachineFunction &MF = DAG.getMachineFunction();
 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
 SDLoc DL(Op);
 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
-getPointerTy());
+getPointerTy(MF.getDataLayout()));
 // vastart just stores the address of the VarArgsFrameIndex slot into the
 // memory location argument.
 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
 unsigned Align = Node->getConstantOperandVal(3);
 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
 SDLoc DL(Node);
 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
-SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
+SDValue VAListLoad =
-MachinePointerInfo(SV), false, false, false,
+DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
-0);
+MachinePointerInfo(SV), false, false, false, 0);
 SDValue VAList = VAListLoad;
 // Re-align the pointer if necessary.
 // It should only ever be necessary for 64-bit types on O32 since the minimum
 // argument alignment is the same as the maximum type alignment for N32/N64.
 //        va_args for the i64 on O32 case).
 if (Align > getMinStackArgumentAlignment()) {
 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
-DAG.getConstant(Align - 1,
+DAG.getConstant(Align - 1, DL, VAList.getValueType()));
+VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
+DAG.getConstant(-(int64_t)Align, DL,
 VAList.getValueType()));
-VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
-DAG.getConstant(-(int64_t)Align,
-VAList.getValueType()));
 }
 // Increment the pointer, VAList, to the next vaarg.
-unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
+auto &TD = DAG.getDataLayout();
+unsigned ArgSizeInBytes =
+TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
-DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
+DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes,
-VAList.getValueType()));
+ArgSlotSizeInBytes),
+DL, VAList.getValueType()));
 // Store the incremented VAList to the legalized pointer
 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
 MachinePointerInfo(SV), false, false, 0);
 // In big-endian mode we must adjust the pointer when the load size is smaller
 // the correct half of the slot, and reduce the alignment from 8 (slot
 // alignment) down to 4 (type alignment).
 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
-DAG.getIntPtrConstant(Adjustment));
+DAG.getIntPtrConstant(Adjustment, DL));
 }
 // Load the actual argument out of the pointer VAList
 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
 false, 0);
 }
 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
 bool HasExtractInsert) {
 EVT TyX = Op.getOperand(0).getValueType();
 EVT TyY = Op.getOperand(1).getValueType();
-SDValue Const1 = DAG.getConstant(1, MVT::i32);
-SDValue Const31 = DAG.getConstant(31, MVT::i32);
 SDLoc DL(Op);
+SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
+SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
 SDValue Res;
 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
 // to i32.
 SDValue X = (TyX == MVT::f32) ?
 if (TyX == MVT::f32)
 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
-Op.getOperand(0), DAG.getConstant(0, MVT::i32));
+Op.getOperand(0),
+DAG.getConstant(0, DL, MVT::i32));
 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
 }
 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
 bool HasExtractInsert) {
 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
-SDValue Const1 = DAG.getConstant(1, MVT::i32);
 SDLoc DL(Op);
+SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
 // Bitcast to integer nodes.
 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
 if (HasExtractInsert) {
 // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
 // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
-DAG.getConstant(WidthY - 1, MVT::i32), Const1);
+DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
 if (WidthX > WidthY)
 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
 else if (WidthY > WidthX)
 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
-DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
+DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
+X);
 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
 }
 // (d)sll SllX, X, 1
 // (d)srl SrlX, SllX, 1
 // (d)sll SllY, SrlX, width(Y)-1
 // or     Or, SrlX, SllY
 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
-DAG.getConstant(WidthY - 1, MVT::i32));
+DAG.getConstant(WidthY - 1, DL, MVT::i32));
 if (WidthX > WidthY)
 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
 else if (WidthY > WidthX)
 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
-DAG.getConstant(WidthX - 1, MVT::i32));
+DAG.getConstant(WidthX - 1, DL, MVT::i32));
 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
 }
 SDValue
 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
 DAG.getRegister(OffsetReg, Ty),
-DAG.getRegister(AddrReg, getPointerTy()),
+DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
 Chain.getValue(1));
 }
 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
 SelectionDAG &DAG) const {
 // FIXME: Need pseudo-fence for 'singlethread' fences
 // FIXME: Set SType for weaker fences where supported/appropriate.
 unsigned SType = 0;
 SDLoc DL(Op);
 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
-DAG.getConstant(SType, MVT::i32));
+DAG.getConstant(SType, DL, MVT::i32));
 }
 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
 SelectionDAG &DAG) const {
 SDLoc DL(Op);
 //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
 // else:
 //  lo = 0
 //  hi = (shl lo, shamt[4:0])
 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
-DAG.getConstant(-1, MVT::i32));
+DAG.getConstant(-1, DL, MVT::i32));
 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
-DAG.getConstant(1, VT));
+DAG.getConstant(1, DL, VT));
 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
-DAG.getConstant(0x20, MVT::i32));
+DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
-DAG.getConstant(0, VT), ShiftLeftLo);
+DAG.getConstant(0, DL, VT), ShiftLeftLo);
 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
 SDValue Ops[2] = {Lo, Hi};
 return DAG.getMergeValues(Ops, DL);
 }
 //   hi = (sra hi, 31)
 //  else:
 //   lo = (srl hi, shamt[4:0])
 //   hi = 0
 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
-DAG.getConstant(-1, MVT::i32));
+DAG.getConstant(-1, DL, MVT::i32));
 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
-DAG.getConstant(1, VT));
+DAG.getConstant(1, DL, VT));
 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
 DL, VT, Hi, Shamt);
 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
-DAG.getConstant(0x20, MVT::i32));
+DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
-SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
+SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
+DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
-IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
+IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
 SDValue Ops[2] = {Lo, Hi};
 return DAG.getMergeValues(Ops, DL);
 }
 SDLoc DL(LD);
 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
 if (Offset)
 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
-DAG.getConstant(Offset, BasePtrVT));
+DAG.getConstant(Offset, DL, BasePtrVT));
 SDValue Ops[] = { Chain, Ptr, Src };
 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
 LD->getMemOperand());
 }
 //  (set tmp0, (lwl (add baseptr, 3), undef))
 //  (set tmp1, (lwr baseptr, tmp0))
 //  (set tmp2, (shl tmp1, 32))
 //  (set dst, (srl tmp2, 32))
 SDLoc DL(LD);
-SDValue Const32 = DAG.getConstant(32, MVT::i32);
+SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
 SDValue Ops[] = { SRL, LWR.getValue(1) };
 return DAG.getMergeValues(Ops, DL);
 }
 SDLoc DL(SD);
 SDVTList VTList = DAG.getVTList(MVT::Other);
 if (Offset)
 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
-DAG.getConstant(Offset, BasePtrVT));
+DAG.getConstant(Offset, DL, BasePtrVT));
 SDValue Ops[] = { Chain, Value, Ptr };
 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
 SD->getMemOperand());
 }
 // the old stack pointer.
 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
 EVT ValTy = Op->getValueType(0);
 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
-return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
+SDLoc DL(Op);
-DAG.getConstant(0, ValTy));
+return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
+DAG.getConstant(0, DL, ValTy));
 }
 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
 SelectionDAG &DAG) const {
 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
 //===----------------------------------------------------------------------===//
 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
-CCState &State, const MCPhysReg *F64Regs) {
+CCState &State, ArrayRef<MCPhysReg> F64Regs) {
 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
 State.getMachineFunction().getSubtarget());
-static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
 // Do not process byval args here.
 unsigned Reg;
 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
 // is true: function is vararg, argument is 3rd or higher, there is previous
 // argument which is not f32 or f64.
-bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
+bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
-|| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
+State.getFirstUnallocated(F32Regs) != ValNo;
 unsigned OrigAlign = ArgFlags.getOrigAlign();
 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
-Reg = State.AllocateReg(IntRegs, IntRegsSize);
+Reg = State.AllocateReg(IntRegs);
 // If this is the first part of an i64 arg,
 // the allocated register must be either A0 or A2.
 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
-Reg = State.AllocateReg(IntRegs, IntRegsSize);
+Reg = State.AllocateReg(IntRegs);
 LocVT = MVT::i32;
 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
 // Allocate int register and shadow next int register. If first
 // available register is Mips::A1 or Mips::A3, shadow it too.
-Reg = State.AllocateReg(IntRegs, IntRegsSize);
+Reg = State.AllocateReg(IntRegs);
 if (Reg == Mips::A1 || Reg == Mips::A3)
-Reg = State.AllocateReg(IntRegs, IntRegsSize);
+Reg = State.AllocateReg(IntRegs);
-State.AllocateReg(IntRegs, IntRegsSize);
+State.AllocateReg(IntRegs);
 LocVT = MVT::i32;
 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
 // we are guaranteed to find an available float register
 if (ValVT == MVT::f32) {
-Reg = State.AllocateReg(F32Regs, FloatRegsSize);
+Reg = State.AllocateReg(F32Regs);
 // Shadow int register
-State.AllocateReg(IntRegs, IntRegsSize);
+State.AllocateReg(IntRegs);
 } else {
-Reg = State.AllocateReg(F64Regs, FloatRegsSize);
+Reg = State.AllocateReg(F64Regs);
 // Shadow int registers
-unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
+unsigned Reg2 = State.AllocateReg(IntRegs);
 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
-State.AllocateReg(IntRegs, IntRegsSize);
+State.AllocateReg(IntRegs);
-State.AllocateReg(IntRegs, IntRegsSize);
+State.AllocateReg(IntRegs);
 }
 } else
 llvm_unreachable("Cannot handle this ValVT.");
 if (!Reg) {
 SDValue
 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
 SDValue Chain, SDValue Arg, SDLoc DL,
 bool IsTailCall, SelectionDAG &DAG) const {
 if (!IsTailCall) {
-SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
+SDValue PtrOff =
-DAG.getIntPtrConstant(Offset));
+DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
+DAG.getIntPtrConstant(Offset, DL));
 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
 false, 0);
 }
 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
-SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
+SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
 /*isVolatile=*/ true, false, 0);
 }
 void MipsTargetLowering::
 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
 RegsToPass[i].second.getValueType()));
 // Add a register mask operand representing the call-preserved registers.
 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
-const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
+const uint32_t *Mask =
+TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
 assert(Mask && "Missing call preserved mask for calling convention");
 if (Subtarget.inMips16HardFloat()) {
 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
 llvm::StringRef Sym = G->getGlobal()->getName();
 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
 // Chain is the output chain of the last Load/Store or CopyToReg node.
 // ByValChain is the output chain of the last Memcpy node created for copying
 // byval arguments to the stack.
 unsigned StackAlignment = TFL->getStackAlignment();
 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
-SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
+SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
 if (!IsTailCall)
 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
-SDValue StackPtr = DAG.getCopyFromReg(
+SDValue StackPtr =
-Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy());
+DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
+getPointerTy(DAG.getDataLayout()));
 // With EABI is it possible to have 16 args on registers.
 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
 SmallVector<SDValue, 8> MemOpChains;
 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
 (ValVT == MVT::i64 && LocVT == MVT::f64))
 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
-Arg, DAG.getConstant(0, MVT::i32));
+Arg, DAG.getConstant(0, DL, MVT::i32));
 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
-Arg, DAG.getConstant(1, MVT::i32));
+Arg, DAG.getConstant(1, DL, MVT::i32));
 if (!Subtarget.isLittle())
 std::swap(Lo, Hi);
 unsigned LocRegLo = VA.getLocReg();
 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
 if (UseUpperBits) {
 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
 Arg = DAG.getNode(
 ISD::SHL, DL, VA.getLocVT(), Arg,
-DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
+DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
 }
 // Arguments that can be passed on register must be kept at
 // RegsToPass vector
 if (VA.isRegLoc()) {
 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
 FuncInfo->callPtrInfo(Val));
 IsCallReloc = true;
 }
 } else
-Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
+Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
+getPointerTy(DAG.getDataLayout()), 0,
 MipsII::MO_NO_FLAG);
 GlobalOrExternal = true;
 }
 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
 const char *Sym = S->getSymbol();
 if (!ABI.IsN64() && !IsPIC) // !N64 && static
-Callee =
+Callee = DAG.getTargetExternalSymbol(
-DAG.getTargetExternalSymbol(Sym, getPointerTy(), MipsII::MO_NO_FLAG);
+Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
 else if (LargeGOT) {
 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
 MipsII::MO_CALL_LO16, Chain,
 FuncInfo->callPtrInfo(Sym));
 IsCallReloc = true;
 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
 SDValue InFlag = Chain.getValue(1);
 // Create the CALLSEQ_END node.
 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
-DAG.getIntPtrConstant(0, true), InFlag, DL);
+DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
 InFlag = Chain.getValue(1);
 // Handle result values, copying them out of physregs into vregs that we
 // return.
 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
 unsigned Shift =
 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
 Val = DAG.getNode(
 Shift, DL, VA.getLocVT(), Val,
-DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
+DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
 }
 switch (VA.getLocInfo()) {
 default:
 llvm_unreachable("Unknown loc info!");
 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
 unsigned Opcode =
 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
 Val = DAG.getNode(
 Opcode, DL, VA.getLocVT(), Val,
-DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
+DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
 break;
 }
 }
 // If this is an value smaller than the argument slot size (32-bit for O32,
 if (ABI.IsO32()) {
 // We ought to be able to use LocVT directly but O32 sets it to i32
 // when allocating floating point values to integer registers.
 // This shouldn't influence how we load the value into registers unless
-// we are targetting softfloat.
+// we are targeting softfloat.
-if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
+if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
 LocVT = VA.getValVT();
 }
 // sanity check
 assert(VA.isMemLoc());
 // The stack pointer offset is relative to the caller stack frame.
 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
 VA.getLocMemOffset(), true);
 // Create load nodes to retrieve arguments from the stack
-SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
+SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
-SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
+SDValue ArgValue = DAG.getLoad(
-MachinePointerInfo::getFixedStack(FI),
+LocVT, DL, Chain, FIN,
-false, false, false, 0);
+MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
+false, false, false, 0);
 OutChains.push_back(ArgValue.getValue(1));
 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
 InVals.push_back(ArgValue);
 const SmallVectorImpl<ISD::OutputArg> &Outs,
 LLVMContext &Context) const {
 SmallVector<CCValAssign, 16> RVLocs;
 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
 return CCInfo.CheckReturn(Outs, RetCC_Mips);
+}
+bool
+MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
+if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
+if (Type == MVT::i32)
+return true;
+}
+return IsSigned;
 }
 SDValue
 MipsTargetLowering::LowerReturn(SDValue Chain,
 CallingConv::ID CallConv, bool IsVarArg,
 if (UseUpperBits) {
 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
 Val = DAG.getNode(
 ISD::SHL, DL, VA.getLocVT(), Val,
-DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
+DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
 }
 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
 // Guarantee that all emitted copies are stuck together with flags.
 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 unsigned Reg = MipsFI->getSRetReturnReg();
 if (!Reg)
 llvm_unreachable("sret virtual register not created in the entry block");
-SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
+SDValue Val =
+DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
 Flag = Chain.getValue(1);
-RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
+RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
 }
 RetOps[0] = Chain;  // Update chain.
 // Add the flag if we have it.
 //                           Mips Inline Assembly Support
 //===----------------------------------------------------------------------===//
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
-MipsTargetLowering::ConstraintType MipsTargetLowering::
+MipsTargetLowering::ConstraintType
-getConstraintType(const std::string &Constraint) const
+MipsTargetLowering::getConstraintType(StringRef Constraint) const {
-{
 // Mips specific constraints
 // GCC config/mips/constraints.md
 //
 // 'd' : An address register. Equivalent to r
 //       unless generating MIPS16 code.
 return C_RegisterClass;
 case 'R':
 return C_Memory;
 }
 }
+if (Constraint == "ZC")
+return C_Memory;
 return TargetLowering::getConstraintType(Constraint);
 }
 /// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// This is a helper function to parse a physical register string and split it
 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
 /// that is returned indicates whether parsing was successful. The second flag
 /// is true if the numeric part exists.
-static std::pair<bool, bool>
+static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
-parsePhysicalReg(StringRef C, std::string &Prefix,
+unsigned long long &Reg) {
-unsigned long long &Reg) {
 if (C.front() != '{' || C.back() != '}')
 return std::make_pair(false, false);
 // Search for the first numeric character.
 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
 I = std::find_if(B, E, std::ptr_fun(isdigit));
-Prefix.assign(B, I - B);
+Prefix = StringRef(B, I - B);
 // The second flag is set to false if no numeric characters were found.
 if (I == E)
 return std::make_pair(true, false);
 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
 const TargetRegisterInfo *TRI =
 Subtarget.getRegisterInfo();
 const TargetRegisterClass *RC;
-std::string Prefix;
+StringRef Prefix;
 unsigned long long Reg;
 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
 if (!R.first)
 return std::make_pair(0U, nullptr);
 RC = TRI->getRegClass(Prefix == "hi" ?
 Mips::HI32RegClassID : Mips::LO32RegClassID);
 return std::make_pair(*(RC->begin()), RC);
-} else if (Prefix.compare(0, 4, "$msa") == 0) {
+} else if (Prefix.startswith("$msa")) {
 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
 // No numeric characters follow the name.
 if (R.second)
 return std::make_pair(0U, nullptr);
 }
 /// Given a register class constraint, like 'r', if this corresponds directly
 /// to an LLVM register class, return a register of 0 and the register class
 /// pointer.
-std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
+std::pair<unsigned, const TargetRegisterClass *>
-getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
+MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
-{
+StringRef Constraint,
+MVT VT) const {
 if (Constraint.size() == 1) {
 switch (Constraint[0]) {
 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
 case 'y': // Same as 'r'. Exists for compatibility.
 case 'r':
 R = parseRegForInlineAsmConstraint(Constraint, VT);
 if (R.second)
 return R;
-return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
+return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 /// vector.  If it is invalid, don't add anything to Ops.
 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
 std::string &Constraint,
 std::vector<SDValue>&Ops,
 SelectionDAG &DAG) const {
+SDLoc DL(Op);
 SDValue Result;
 // Only support length 1 constraints for now.
 if (Constraint.length() > 1) return;
 // If this fails, the parent routine will give an error
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getSExtValue();
 if (isInt<16>(Val)) {
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 case 'J': // integer zero
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getZExtValue();
 if (Val == 0) {
-Result = DAG.getTargetConstant(0, Type);
+Result = DAG.getTargetConstant(0, DL, Type);
 break;
 }
 }
 return;
 case 'K': // unsigned 16 bit immediate
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 uint64_t Val = (uint64_t)C->getZExtValue();
 if (isUInt<16>(Val)) {
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 case 'L': // signed 32 bit immediate where lower 16 bits are 0
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getSExtValue();
 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 case 'N': // immediate in the range of -65535 to -1 (inclusive)
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getSExtValue();
 if ((Val >= -65535) && (Val <= -1)) {
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 case 'O': // signed 15 bit immediate
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getSExtValue();
 if ((isInt<15>(Val))) {
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 case 'P': // immediate in the range of 1 to 65535 (inclusive)
 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 EVT Type = Op.getValueType();
 int64_t Val = C->getSExtValue();
 if ((Val <= 65535) && (Val >= 1)) {
-Result = DAG.getTargetConstant(Val, Type);
+Result = DAG.getTargetConstant(Val, DL, Type);
 break;
 }
 }
 return;
 }
 }
 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
-bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
+bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
-Type *Ty) const {
+const AddrMode &AM, Type *Ty,
+unsigned AS) const {
 // No global is ever allowed as a base.
 if (AM.BaseGV)
 return false;
 switch (AM.Scale) {
 unsigned MipsTargetLowering::getJumpTableEncoding() const {
 if (ABI.IsN64())
 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
 return TargetLowering::getJumpTableEncoding();
+}
+bool MipsTargetLowering::useSoftFloat() const {
+return Subtarget.useSoftFloat();
 }
 void MipsTargetLowering::copyByValRegs(
 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
 else
 FrameObjOffset = VA.getLocMemOffset();
 // Create frame object.
-EVT PtrTy = getPointerTy();
+EVT PtrTy = getPointerTy(DAG.getDataLayout());
 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
 InVals.push_back(FIN);
 if (!NumRegs)
 for (unsigned I = 0; I < NumRegs; ++I) {
 unsigned ArgReg = ByValArgRegs[FirstReg + I];
 unsigned VReg = addLiveIn(MF, ArgReg, RC);
 unsigned Offset = I * GPRSizeInBytes;
 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
-DAG.getConstant(Offset, PtrTy));
+DAG.getConstant(Offset, DL, PtrTy));
 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
 StorePtr, MachinePointerInfo(FuncArg, Offset),
 false, false, 0);
 OutChains.push_back(Store);
 }
 const CCValAssign &VA) const {
 unsigned ByValSizeInBytes = Flags.getByValSize();
 unsigned OffsetInBytes = 0; // From beginning of struct
 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
-EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
+EVT PtrTy = getPointerTy(DAG.getDataLayout()),
+RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
 unsigned NumRegs = LastReg - FirstReg;
 if (NumRegs) {
-const ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
+ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
 unsigned I = 0;
 // Copy words to registers.
 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
-DAG.getConstant(OffsetInBytes, PtrTy));
+DAG.getConstant(OffsetInBytes, DL, PtrTy));
 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
 MachinePointerInfo(), false, false, false,
 Alignment);
 MemOpChains.push_back(LoadVal.getValue(1));
 unsigned ArgReg = ArgRegs[FirstReg + I];
 if (RemainingSizeInBytes < LoadSizeInBytes)
 continue;
 // Load subword.
 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
-DAG.getConstant(OffsetInBytes, PtrTy));
+DAG.getConstant(OffsetInBytes, DL,
+PtrTy));
 SDValue LoadVal = DAG.getExtLoad(
 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
 Alignment);
 MemOpChains.push_back(LoadVal.getValue(1));
 Shamt = TotalBytesLoaded * 8;
 else
 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
-DAG.getConstant(Shamt, MVT::i32));
+DAG.getConstant(Shamt, DL, MVT::i32));
 if (Val.getNode())
 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
 else
 Val = Shift;
 }
 // Copy remainder of byval arg to it with memcpy.
 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
-DAG.getConstant(OffsetInBytes, PtrTy));
+DAG.getConstant(OffsetInBytes, DL, PtrTy));
 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
-DAG.getIntPtrConstant(VA.getLocMemOffset()));
+DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
-Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
+Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
+DAG.getConstant(MemCpySize, DL, PtrTy),
 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
+/*isTailCall=*/false,
 MachinePointerInfo(), MachinePointerInfo());
 MemOpChains.push_back(Chain);
 }
 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
 SDValue Chain, SDLoc DL,
 SelectionDAG &DAG,
 CCState &State) const {
-const ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
+ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
-unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
+unsigned Idx = State.getFirstUnallocated(ArgRegs);
 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
 const TargetRegisterClass *RC = getRegClassFor(RegTy);
 MachineFunction &MF = DAG.getMachineFunction();
 MachineFrameInfo *MFI = MF.getFrameInfo();
 for (unsigned I = Idx; I < ArgRegs.size();
 ++I, VaArgOffset += RegSizeInBytes) {
 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
-SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
+SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
 MachinePointerInfo(), false, false, 0);
 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
 (Value *)nullptr);
 OutChains.push_back(Store);
 unsigned FirstReg = 0;
 unsigned NumRegs = 0;
 if (State->getCallingConv() != CallingConv::Fast) {
 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
-const ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
+ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
 // FIXME: The O32 case actually describes no shadow registers.
 const MCPhysReg *ShadowRegs =
 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
 // We used to check the size as well but we can't do that anymore since
 // CCState::HandleByVal() rounds up the size after calling this function.
 assert(!(Align % RegSizeInBytes) &&
 "Byval argument's alignment should be a multiple of"
 "RegSizeInBytes.");
-FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
+FirstReg = State->getFirstUnallocated(IntArgRegs);
 // If Align > RegSizeInBytes, the first arg register must be even.
 // FIXME: This condition happens to do the right thing but it's not the
 //        right way to test it. We want to check that the stack frame offset
 //        of the register is aligned.
 return BB;
 }
 // FIXME? Maybe this could be a TableGen attribute on some registers and
 // this table could be generated automatically from RegInfo.
-unsigned MipsTargetLowering::getRegisterByName(const char* RegName,
+unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
-EVT VT) const {
+SelectionDAG &DAG) const {
 // Named registers is expected to be fairly rare. For now, just support $28
 // since the linux kernel uses it.
 if (Subtarget.isGP64bit()) {
 unsigned Reg = StringSwitch<unsigned>(RegName)
 .Case("$28", Mips::GP_64)

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Mips/MipsISelLowering.cpp @ 95:afa8332a0e37 LLVM3.8