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comparison lib/Target/NVPTX/NVPTXISelLowering.h @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
19 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h" 20 #include "llvm/Target/TargetLowering.h"
21 21
22 namespace llvm { 22 namespace llvm {
23 namespace NVPTXISD { 23 namespace NVPTXISD {
24 enum NodeType { 24 enum NodeType : unsigned {
25 // Start the numbering from where ISD NodeType finishes. 25 // Start the numbering from where ISD NodeType finishes.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 Wrapper, 27 Wrapper,
28 CALL, 28 CALL,
29 RET_FLAG, 29 RET_FLAG,
454 /// isLegalAddressingMode - Return true if the addressing mode represented 454 /// isLegalAddressingMode - Return true if the addressing mode represented
455 /// by AM is legal for this target, for a load/store of the specified type 455 /// by AM is legal for this target, for a load/store of the specified type
456 /// Used to guide target specific optimizations, like loop strength 456 /// Used to guide target specific optimizations, like loop strength
457 /// reduction (LoopStrengthReduce.cpp) and memory optimization for 457 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
458 /// address mode (CodeGenPrepare.cpp) 458 /// address mode (CodeGenPrepare.cpp)
459 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 459 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
460 unsigned AS) const override;
461
462 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
463 // Truncating 64-bit to 32-bit is free in SASS.
464 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
465 return false;
466 return SrcTy->getPrimitiveSizeInBits() == 64 &&
467 DstTy->getPrimitiveSizeInBits() == 32;
468 }
460 469
461 /// getFunctionAlignment - Return the Log2 alignment of this function. 470 /// getFunctionAlignment - Return the Log2 alignment of this function.
462 unsigned getFunctionAlignment(const Function *F) const; 471 unsigned getFunctionAlignment(const Function *F) const;
463 472
464 EVT getSetCCResultType(LLVMContext &Ctx, EVT VT) const override { 473 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
474 EVT VT) const override {
465 if (VT.isVector()) 475 if (VT.isVector())
466 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements()); 476 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
467 return MVT::i1; 477 return MVT::i1;
468 } 478 }
469 479
470 ConstraintType 480 ConstraintType getConstraintType(StringRef Constraint) const override;
471 getConstraintType(const std::string &Constraint) const override;
472 std::pair<unsigned, const TargetRegisterClass *> 481 std::pair<unsigned, const TargetRegisterClass *>
473 getRegForInlineAsmConstraint(const std::string &Constraint, 482 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
474 MVT VT) const override; 483 StringRef Constraint, MVT VT) const override;
475 484
476 SDValue LowerFormalArguments( 485 SDValue LowerFormalArguments(
477 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 486 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
478 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, 487 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
479 SmallVectorImpl<SDValue> &InVals) const override; 488 SmallVectorImpl<SDValue> &InVals) const override;
480 489
481 SDValue LowerCall(CallLoweringInfo &CLI, 490 SDValue LowerCall(CallLoweringInfo &CLI,
482 SmallVectorImpl<SDValue> &InVals) const override; 491 SmallVectorImpl<SDValue> &InVals) const override;
483 492
484 std::string getPrototype(Type *, const ArgListTy &, 493 std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
485 const SmallVectorImpl<ISD::OutputArg> &, 494 const SmallVectorImpl<ISD::OutputArg> &,
486 unsigned retAlignment, 495 unsigned retAlignment,
487 const ImmutableCallSite *CS) const; 496 const ImmutableCallSite *CS) const;
488 497
489 SDValue 498 SDValue
497 SelectionDAG &DAG) const override; 506 SelectionDAG &DAG) const override;
498 507
499 const NVPTXTargetMachine *nvTM; 508 const NVPTXTargetMachine *nvTM;
500 509
501 // PTX always uses 32-bit shift amounts 510 // PTX always uses 32-bit shift amounts
502 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 511 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
512 return MVT::i32;
513 }
503 514
504 TargetLoweringBase::LegalizeTypeAction 515 TargetLoweringBase::LegalizeTypeAction
505 getPreferredVectorAction(EVT VT) const override; 516 getPreferredVectorAction(EVT VT) const override;
506 517
507 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const; 518 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;