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comparison test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
11 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32] 11 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32]
12 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp] 12 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp]
13 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32] 13 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32]
14 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]] 14 ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]]
15 %retval = alloca <16 x float>, align 16 15 %retval = alloca <16 x float>, align 16
16 %0 = load <16 x float>* @T3_retval, align 16 16 %0 = load <16 x float>, <16 x float>* @T3_retval, align 16
17 store <16 x float> %0, <16 x float>* %retval 17 store <16 x float> %0, <16 x float>* %retval
18 %1 = load <16 x float>* %retval 18 %1 = load <16 x float>, <16 x float>* %retval
19 store <16 x float> %1, <16 x float>* %agg.result, align 16 19 store <16 x float> %1, <16 x float>* %agg.result, align 16
20 ret void 20 ret void
21 } 21 }