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comparison test/CodeGen/AArch64/arm64-fast-isel-gv.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s 1 ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
2 2
3 ; Test load/store of global value from global offset table. 3 ; Test load/store of global value from global offset table.
4 @seed = common global i64 0, align 8 4 @seed = common global i64 0, align 8
5 5
6 define void @Initrand() nounwind { 6 define void @Initrand() nounwind {
24 ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]] 24 ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
25 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] 25 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
26 ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff 26 ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
27 ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} 27 ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}
28 ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}} 28 ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
29 %0 = load i64* @seed, align 8 29 %0 = load i64, i64* @seed, align 8
30 %mul = mul nsw i64 %0, 1309 30 %mul = mul nsw i64 %0, 1309
31 %add = add nsw i64 %mul, 13849 31 %add = add nsw i64 %mul, 13849
32 %and = and i64 %add, 65535 32 %and = and i64 %add, 65535
33 store i64 %and, i64* @seed, align 8 33 store i64 %and, i64* @seed, align 8
34 %1 = load i64* @seed, align 8 34 %1 = load i64, i64* @seed, align 8
35 %conv = trunc i64 %1 to i32 35 %conv = trunc i64 %1 to i32
36 ret i32 %conv 36 ret i32 %conv
37 } 37 }