Mercurial > hg > CbC > CbC_llvm

comparison test/CodeGen/AMDGPU/max-literals.ll @ 95:afa8332a0e37 LLVM3.8

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/max-literals.ll@60c9769439b8
children 1172e4bd9c6f
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3 ; CHECK-LABEL: {{^}}main:
4 ; CHECK: ADD *
5
6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
7 main_body:
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
12 %4 = extractelement <4 x float> %reg2, i32 0
13 %5 = fadd float %0, 2.0
14 %6 = fadd float %1, 3.0
15 %7 = fadd float %2, 4.0
16 %8 = fadd float %3, 5.0
17 %9 = bitcast float %4 to i32
18 %10 = mul i32 %9, 6
19 %11 = bitcast i32 %10 to float
20 %12 = insertelement <4 x float> undef, float %5, i32 0
21 %13 = insertelement <4 x float> %12, float %6, i32 1
22 %14 = insertelement <4 x float> %13, float %7, i32 2
23 %15 = insertelement <4 x float> %14, float %8, i32 3
24 %16 = insertelement <4 x float> %15, float %11, i32 3
25
26 %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16)
27 %18 = insertelement <4 x float> undef, float %17, i32 0
28 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
29 ret void
30 }
31
32 ; CHECK-LABEL: {{^}}main2:
33 ; CHECK-NOT: ADD *
34
35 define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
36 main_body:
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
41 %4 = extractelement <4 x float> %reg2, i32 0
42 %5 = fadd float %0, 2.0
43 %6 = fadd float %1, 3.0
44 %7 = fadd float %2, 4.0
45 %8 = fadd float %3, 2.0
46 %9 = bitcast float %4 to i32
47 %10 = mul i32 %9, 6
48 %11 = bitcast i32 %10 to float
49 %12 = insertelement <4 x float> undef, float %5, i32 0
50 %13 = insertelement <4 x float> %12, float %6, i32 1
51 %14 = insertelement <4 x float> %13, float %7, i32 2
52 %15 = insertelement <4 x float> %14, float %8, i32 3
53 %16 = insertelement <4 x float> %15, float %11, i32 3
54
55 %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16)
56 %18 = insertelement <4 x float> undef, float %17, i32 0
57 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
58 ret void
59 }
60
61 ; Function Attrs: readnone
62 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
63
64 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
65
66 attributes #0 = { "ShaderType"="1" }
67 attributes #1 = { readnone }