Mercurial > hg > CbC > CbC_llvm
comparison test/CodeGen/AMDGPU/pv-packing.ll @ 95:afa8332a0e37 LLVM3.8
LLVM 3.8
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
---|---|
date | Tue, 13 Oct 2015 17:48:58 +0900 |
parents | |
children | 1172e4bd9c6f |
comparison
equal
deleted
inserted
replaced
84:f3e34b893a5f | 95:afa8332a0e37 |
---|---|
1 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s | |
2 | |
3 ;CHECK: DOT4 T{{[0-9]\.X}} | |
4 ;CHECK: MULADD_IEEE * T{{[0-9]\.W}} | |
5 | |
6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { | |
7 main_body: | |
8 %0 = extractelement <4 x float> %reg1, i32 0 | |
9 %1 = extractelement <4 x float> %reg1, i32 1 | |
10 %2 = extractelement <4 x float> %reg1, i32 2 | |
11 %3 = extractelement <4 x float> %reg2, i32 0 | |
12 %4 = extractelement <4 x float> %reg2, i32 1 | |
13 %5 = extractelement <4 x float> %reg2, i32 2 | |
14 %6 = extractelement <4 x float> %reg3, i32 0 | |
15 %7 = extractelement <4 x float> %reg3, i32 1 | |
16 %8 = extractelement <4 x float> %reg3, i32 2 | |
17 %9 = load <4 x float>, <4 x float> addrspace(8)* null | |
18 %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) | |
19 %11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9) | |
20 %12 = fmul float %0, %3 | |
21 %13 = fadd float %12, %6 | |
22 %14 = fmul float %1, %4 | |
23 %15 = fadd float %14, %7 | |
24 %16 = fmul float %2, %5 | |
25 %17 = fadd float %16, %8 | |
26 %18 = fmul float %11, %11 | |
27 %19 = fadd float %18, %0 | |
28 %20 = insertelement <4 x float> undef, float %13, i32 0 | |
29 %21 = insertelement <4 x float> %20, float %15, i32 1 | |
30 %22 = insertelement <4 x float> %21, float %17, i32 2 | |
31 %23 = insertelement <4 x float> %22, float %19, i32 3 | |
32 %24 = call float @llvm.AMDGPU.dp4(<4 x float> %23, <4 x float> %10) | |
33 %25 = insertelement <4 x float> undef, float %24, i32 0 | |
34 call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2) | |
35 ret void | |
36 } | |
37 | |
38 ; Function Attrs: readnone | |
39 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 | |
40 | |
41 | |
42 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) | |
43 | |
44 attributes #0 = { "ShaderType"="1" } | |
45 attributes #1 = { readnone } |