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comparison test/CodeGen/SystemZ/asm-18.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children c2174574ed3a
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
1 ; Test high-word operations, using "h" constraints to force a high 1 ; Test high-word operations, using "h" constraints to force a high
2 ; register and "r" constraints to force a low register. 2 ; register and "r" constraints to force a low register.
3 ; 3 ;
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as | FileCheck %s 4 ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \
5 ; RUN: -no-integrated-as | FileCheck %s
5 6
6 ; Test loads and stores involving mixtures of high and low registers. 7 ; Test loads and stores involving mixtures of high and low registers.
7 define void @f1(i32 *%ptr1, i32 *%ptr2) { 8 define void @f1(i32 *%ptr1, i32 *%ptr2) {
8 ; CHECK-LABEL: f1: 9 ; CHECK-LABEL: f1:
9 ; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2) 10 ; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2)
14 ; CHECK-DAG: stfh [[REG1]], 0(%r2) 15 ; CHECK-DAG: stfh [[REG1]], 0(%r2)
15 ; CHECK-DAG: st [[REG2]], 0(%r3) 16 ; CHECK-DAG: st [[REG2]], 0(%r3)
16 ; CHECK-DAG: stfh [[REG3]], 4096(%r2) 17 ; CHECK-DAG: stfh [[REG3]], 4096(%r2)
17 ; CHECK-DAG: sty [[REG4]], 524284(%r3) 18 ; CHECK-DAG: sty [[REG4]], 524284(%r3)
18 ; CHECK: br %r14 19 ; CHECK: br %r14
19 %ptr3 = getelementptr i32 *%ptr1, i64 1024 20 %ptr3 = getelementptr i32, i32 *%ptr1, i64 1024
20 %ptr4 = getelementptr i32 *%ptr2, i64 131071 21 %ptr4 = getelementptr i32, i32 *%ptr2, i64 131071
21 %old1 = load i32 *%ptr1 22 %old1 = load i32 , i32 *%ptr1
22 %old2 = load i32 *%ptr2 23 %old2 = load i32 , i32 *%ptr2
23 %old3 = load i32 *%ptr3 24 %old3 = load i32 , i32 *%ptr3
24 %old4 = load i32 *%ptr4 25 %old4 = load i32 , i32 *%ptr4
25 %res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3", 26 %res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3",
26 "=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4) 27 "=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4)
27 %new1 = extractvalue { i32, i32, i32, i32 } %res, 0 28 %new1 = extractvalue { i32, i32, i32, i32 } %res, 0
28 %new2 = extractvalue { i32, i32, i32, i32 } %res, 1 29 %new2 = extractvalue { i32, i32, i32, i32 } %res, 1
29 %new3 = extractvalue { i32, i32, i32, i32 } %res, 2 30 %new3 = extractvalue { i32, i32, i32, i32 } %res, 2
58 ; CHECK-DAG: lb [[REG2:%r[0-5]]], 0(%r3) 59 ; CHECK-DAG: lb [[REG2:%r[0-5]]], 0(%r3)
59 ; CHECK-DAG: lbh [[REG3:%r[0-5]]], 4096(%r2) 60 ; CHECK-DAG: lbh [[REG3:%r[0-5]]], 4096(%r2)
60 ; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3) 61 ; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3)
61 ; CHECK: blah [[REG1]], [[REG2]] 62 ; CHECK: blah [[REG1]], [[REG2]]
62 ; CHECK: br %r14 63 ; CHECK: br %r14
63 %ptr3 = getelementptr i8 *%ptr1, i64 4096 64 %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
64 %ptr4 = getelementptr i8 *%ptr2, i64 524287 65 %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
65 %val1 = load i8 *%ptr1 66 %val1 = load i8 , i8 *%ptr1
66 %val2 = load i8 *%ptr2 67 %val2 = load i8 , i8 *%ptr2
67 %val3 = load i8 *%ptr3 68 %val3 = load i8 , i8 *%ptr3
68 %val4 = load i8 *%ptr4 69 %val4 = load i8 , i8 *%ptr4
69 %ext1 = sext i8 %val1 to i32 70 %ext1 = sext i8 %val1 to i32
70 %ext2 = sext i8 %val2 to i32 71 %ext2 = sext i8 %val2 to i32
71 %ext3 = sext i8 %val3 to i32 72 %ext3 = sext i8 %val3 to i32
72 %ext4 = sext i8 %val4 to i32 73 %ext4 = sext i8 %val4 to i32
73 call void asm sideeffect "blah $0, $1, $2, $3", 74 call void asm sideeffect "blah $0, $1, $2, $3",
82 ; CHECK-DAG: lh [[REG2:%r[0-5]]], 0(%r3) 83 ; CHECK-DAG: lh [[REG2:%r[0-5]]], 0(%r3)
83 ; CHECK-DAG: lhh [[REG3:%r[0-5]]], 4096(%r2) 84 ; CHECK-DAG: lhh [[REG3:%r[0-5]]], 4096(%r2)
84 ; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3) 85 ; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3)
85 ; CHECK: blah [[REG1]], [[REG2]] 86 ; CHECK: blah [[REG1]], [[REG2]]
86 ; CHECK: br %r14 87 ; CHECK: br %r14
87 %ptr3 = getelementptr i16 *%ptr1, i64 2048 88 %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
88 %ptr4 = getelementptr i16 *%ptr2, i64 262143 89 %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
89 %val1 = load i16 *%ptr1 90 %val1 = load i16 , i16 *%ptr1
90 %val2 = load i16 *%ptr2 91 %val2 = load i16 , i16 *%ptr2
91 %val3 = load i16 *%ptr3 92 %val3 = load i16 , i16 *%ptr3
92 %val4 = load i16 *%ptr4 93 %val4 = load i16 , i16 *%ptr4
93 %ext1 = sext i16 %val1 to i32 94 %ext1 = sext i16 %val1 to i32
94 %ext2 = sext i16 %val2 to i32 95 %ext2 = sext i16 %val2 to i32
95 %ext3 = sext i16 %val3 to i32 96 %ext3 = sext i16 %val3 to i32
96 %ext4 = sext i16 %val4 to i32 97 %ext4 = sext i16 %val4 to i32
97 call void asm sideeffect "blah $0, $1, $2, $3", 98 call void asm sideeffect "blah $0, $1, $2, $3",
106 ; CHECK-DAG: llc [[REG2:%r[0-5]]], 0(%r3) 107 ; CHECK-DAG: llc [[REG2:%r[0-5]]], 0(%r3)
107 ; CHECK-DAG: llch [[REG3:%r[0-5]]], 4096(%r2) 108 ; CHECK-DAG: llch [[REG3:%r[0-5]]], 4096(%r2)
108 ; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3) 109 ; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3)
109 ; CHECK: blah [[REG1]], [[REG2]] 110 ; CHECK: blah [[REG1]], [[REG2]]
110 ; CHECK: br %r14 111 ; CHECK: br %r14
111 %ptr3 = getelementptr i8 *%ptr1, i64 4096 112 %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
112 %ptr4 = getelementptr i8 *%ptr2, i64 524287 113 %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
113 %val1 = load i8 *%ptr1 114 %val1 = load i8 , i8 *%ptr1
114 %val2 = load i8 *%ptr2 115 %val2 = load i8 , i8 *%ptr2
115 %val3 = load i8 *%ptr3 116 %val3 = load i8 , i8 *%ptr3
116 %val4 = load i8 *%ptr4 117 %val4 = load i8 , i8 *%ptr4
117 %ext1 = zext i8 %val1 to i32 118 %ext1 = zext i8 %val1 to i32
118 %ext2 = zext i8 %val2 to i32 119 %ext2 = zext i8 %val2 to i32
119 %ext3 = zext i8 %val3 to i32 120 %ext3 = zext i8 %val3 to i32
120 %ext4 = zext i8 %val4 to i32 121 %ext4 = zext i8 %val4 to i32
121 call void asm sideeffect "blah $0, $1, $2, $3", 122 call void asm sideeffect "blah $0, $1, $2, $3",
130 ; CHECK-DAG: llh [[REG2:%r[0-5]]], 0(%r3) 131 ; CHECK-DAG: llh [[REG2:%r[0-5]]], 0(%r3)
131 ; CHECK-DAG: llhh [[REG3:%r[0-5]]], 4096(%r2) 132 ; CHECK-DAG: llhh [[REG3:%r[0-5]]], 4096(%r2)
132 ; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3) 133 ; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3)
133 ; CHECK: blah [[REG1]], [[REG2]] 134 ; CHECK: blah [[REG1]], [[REG2]]
134 ; CHECK: br %r14 135 ; CHECK: br %r14
135 %ptr3 = getelementptr i16 *%ptr1, i64 2048 136 %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
136 %ptr4 = getelementptr i16 *%ptr2, i64 262143 137 %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
137 %val1 = load i16 *%ptr1 138 %val1 = load i16 , i16 *%ptr1
138 %val2 = load i16 *%ptr2 139 %val2 = load i16 , i16 *%ptr2
139 %val3 = load i16 *%ptr3 140 %val3 = load i16 , i16 *%ptr3
140 %val4 = load i16 *%ptr4 141 %val4 = load i16 , i16 *%ptr4
141 %ext1 = zext i16 %val1 to i32 142 %ext1 = zext i16 %val1 to i32
142 %ext2 = zext i16 %val2 to i32 143 %ext2 = zext i16 %val2 to i32
143 %ext3 = zext i16 %val3 to i32 144 %ext3 = zext i16 %val3 to i32
144 %ext4 = zext i16 %val4 to i32 145 %ext4 = zext i16 %val4 to i32
145 call void asm sideeffect "blah $0, $1, $2, $3", 146 call void asm sideeffect "blah $0, $1, $2, $3",
159 %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"() 160 %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"()
160 %res1 = extractvalue { i32, i32 } %res, 0 161 %res1 = extractvalue { i32, i32 } %res, 0
161 %res2 = extractvalue { i32, i32 } %res, 1 162 %res2 = extractvalue { i32, i32 } %res, 1
162 %trunc1 = trunc i32 %res1 to i8 163 %trunc1 = trunc i32 %res1 to i8
163 %trunc2 = trunc i32 %res2 to i8 164 %trunc2 = trunc i32 %res2 to i8
164 %ptr3 = getelementptr i8 *%ptr1, i64 4096 165 %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096
165 %ptr4 = getelementptr i8 *%ptr2, i64 524287 166 %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287
166 store i8 %trunc1, i8 *%ptr1 167 store i8 %trunc1, i8 *%ptr1
167 store i8 %trunc2, i8 *%ptr2 168 store i8 %trunc2, i8 *%ptr2
168 store i8 %trunc1, i8 *%ptr3 169 store i8 %trunc1, i8 *%ptr3
169 store i8 %trunc2, i8 *%ptr4 170 store i8 %trunc2, i8 *%ptr4
170 ret void 171 ret void
182 %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"() 183 %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"()
183 %res1 = extractvalue { i32, i32 } %res, 0 184 %res1 = extractvalue { i32, i32 } %res, 0
184 %res2 = extractvalue { i32, i32 } %res, 1 185 %res2 = extractvalue { i32, i32 } %res, 1
185 %trunc1 = trunc i32 %res1 to i16 186 %trunc1 = trunc i32 %res1 to i16
186 %trunc2 = trunc i32 %res2 to i16 187 %trunc2 = trunc i32 %res2 to i16
187 %ptr3 = getelementptr i16 *%ptr1, i64 2048 188 %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048
188 %ptr4 = getelementptr i16 *%ptr2, i64 262143 189 %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143
189 store i16 %trunc1, i16 *%ptr1 190 store i16 %trunc1, i16 *%ptr1
190 store i16 %trunc2, i16 *%ptr2 191 store i16 %trunc2, i16 *%ptr2
191 store i16 %trunc1, i16 *%ptr3 192 store i16 %trunc1, i16 *%ptr3
192 store i16 %trunc2, i16 *%ptr4 193 store i16 %trunc2, i16 *%ptr4
193 ret void 194 ret void
711 ; CHECK: chf [[REG1]], 0(%r2) 712 ; CHECK: chf [[REG1]], 0(%r2)
712 ; CHECK: stepb [[REG2:%r[0-5]]] 713 ; CHECK: stepb [[REG2:%r[0-5]]]
713 ; CHECK: clhf [[REG2]], 0(%r3) 714 ; CHECK: clhf [[REG2]], 0(%r3)
714 ; CHECK: br %r14 715 ; CHECK: br %r14
715 %res1 = call i32 asm "stepa $0", "=h"() 716 %res1 = call i32 asm "stepa $0", "=h"()
716 %load1 = load i32 *%ptr1 717 %load1 = load i32 , i32 *%ptr1
717 %cmp1 = icmp sle i32 %res1, %load1 718 %cmp1 = icmp sle i32 %res1, %load1
718 %sel1 = select i1 %cmp1, i32 0, i32 1 719 %sel1 = select i1 %cmp1, i32 0, i32 1
719 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1) 720 %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1)
720 %load2 = load i32 *%ptr2 721 %load2 = load i32 , i32 *%ptr2
721 %cmp2 = icmp ule i32 %res2, %load2 722 %cmp2 = icmp ule i32 %res2, %load2
722 %sel2 = select i1 %cmp2, i32 0, i32 1 723 %sel2 = select i1 %cmp2, i32 0, i32 1
723 store i32 %sel2, i32 *%ptr1 724 store i32 %sel2, i32 *%ptr1
724 ret void 725 ret void
725 } 726 }
731 ; CHECK: c [[REG1]], 0(%r2) 732 ; CHECK: c [[REG1]], 0(%r2)
732 ; CHECK: stepb [[REG2:%r[0-5]]] 733 ; CHECK: stepb [[REG2:%r[0-5]]]
733 ; CHECK: cl [[REG2]], 0(%r3) 734 ; CHECK: cl [[REG2]], 0(%r3)
734 ; CHECK: br %r14 735 ; CHECK: br %r14
735 %res1 = call i32 asm "stepa $0", "=r"() 736 %res1 = call i32 asm "stepa $0", "=r"()
736 %load1 = load i32 *%ptr1 737 %load1 = load i32 , i32 *%ptr1
737 %cmp1 = icmp sle i32 %res1, %load1 738 %cmp1 = icmp sle i32 %res1, %load1
738 %sel1 = select i1 %cmp1, i32 0, i32 1 739 %sel1 = select i1 %cmp1, i32 0, i32 1
739 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1) 740 %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1)
740 %load2 = load i32 *%ptr2 741 %load2 = load i32 , i32 *%ptr2
741 %cmp2 = icmp ule i32 %res2, %load2 742 %cmp2 = icmp ule i32 %res2, %load2
742 %sel2 = select i1 %cmp2, i32 0, i32 1 743 %sel2 = select i1 %cmp2, i32 0, i32 1
743 store i32 %sel2, i32 *%ptr1 744 store i32 %sel2, i32 *%ptr1
744 ret void 745 ret void
745 } 746 }