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comparison test/CodeGen/SystemZ/vec-move-15.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
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84:f3e34b893a5f 95:afa8332a0e37
1 ; Test vector sign-extending loads.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5 ; Test a v16i1->v16i8 extension.
6 define <16 x i8> @f1(<16 x i1> *%ptr) {
7 ; No expected output, but must compile.
8 %val = load <16 x i1>, <16 x i1> *%ptr
9 %ret = sext <16 x i1> %val to <16 x i8>
10 ret <16 x i8> %ret
11 }
12
13 ; Test a v8i1->v8i16 extension.
14 define <8 x i16> @f2(<8 x i1> *%ptr) {
15 ; No expected output, but must compile.
16 %val = load <8 x i1>, <8 x i1> *%ptr
17 %ret = sext <8 x i1> %val to <8 x i16>
18 ret <8 x i16> %ret
19 }
20
21 ; Test a v8i8->v8i16 extension.
22 define <8 x i16> @f3(<8 x i8> *%ptr) {
23 ; CHECK-LABEL: f3:
24 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
25 ; CHECK: vuphb %v24, [[REG1]]
26 ; CHECK: br %r14
27 %val = load <8 x i8>, <8 x i8> *%ptr
28 %ret = sext <8 x i8> %val to <8 x i16>
29 ret <8 x i16> %ret
30 }
31
32 ; Test a v4i1->v4i32 extension.
33 define <4 x i32> @f4(<4 x i1> *%ptr) {
34 ; No expected output, but must compile.
35 %val = load <4 x i1>, <4 x i1> *%ptr
36 %ret = sext <4 x i1> %val to <4 x i32>
37 ret <4 x i32> %ret
38 }
39
40 ; Test a v4i8->v4i32 extension.
41 define <4 x i32> @f5(<4 x i8> *%ptr) {
42 ; CHECK-LABEL: f5:
43 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
44 ; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
45 ; CHECK: vuphh %v24, [[REG2]]
46 ; CHECK: br %r14
47 %val = load <4 x i8>, <4 x i8> *%ptr
48 %ret = sext <4 x i8> %val to <4 x i32>
49 ret <4 x i32> %ret
50 }
51
52 ; Test a v4i16->v4i32 extension.
53 define <4 x i32> @f6(<4 x i16> *%ptr) {
54 ; CHECK-LABEL: f6:
55 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
56 ; CHECK: vuphh %v24, [[REG1]]
57 ; CHECK: br %r14
58 %val = load <4 x i16>, <4 x i16> *%ptr
59 %ret = sext <4 x i16> %val to <4 x i32>
60 ret <4 x i32> %ret
61 }
62
63 ; Test a v2i1->v2i64 extension.
64 define <2 x i64> @f7(<2 x i1> *%ptr) {
65 ; No expected output, but must compile.
66 %val = load <2 x i1>, <2 x i1> *%ptr
67 %ret = sext <2 x i1> %val to <2 x i64>
68 ret <2 x i64> %ret
69 }
70
71 ; Test a v2i8->v2i64 extension.
72 define <2 x i64> @f8(<2 x i8> *%ptr) {
73 ; CHECK-LABEL: f8:
74 ; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
75 ; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
76 ; CHECK: vuphh [[REG3:%v[0-9]+]], [[REG2]]
77 ; CHECK: vuphf %v24, [[REG3]]
78 ; CHECK: br %r14
79 %val = load <2 x i8>, <2 x i8> *%ptr
80 %ret = sext <2 x i8> %val to <2 x i64>
81 ret <2 x i64> %ret
82 }
83
84 ; Test a v2i16->v2i64 extension.
85 define <2 x i64> @f9(<2 x i16> *%ptr) {
86 ; CHECK-LABEL: f9:
87 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
88 ; CHECK: vuphh [[REG2:%v[0-9]+]], [[REG1]]
89 ; CHECK: vuphf %v24, [[REG2]]
90 ; CHECK: br %r14
91 %val = load <2 x i16>, <2 x i16> *%ptr
92 %ret = sext <2 x i16> %val to <2 x i64>
93 ret <2 x i64> %ret
94 }
95
96 ; Test a v2i32->v2i64 extension.
97 define <2 x i64> @f10(<2 x i32> *%ptr) {
98 ; CHECK-LABEL: f10:
99 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
100 ; CHECK: vuphf %v24, [[REG1]]
101 ; CHECK: br %r14
102 %val = load <2 x i32>, <2 x i32> *%ptr
103 %ret = sext <2 x i32> %val to <2 x i64>
104 ret <2 x i64> %ret
105 }