comparison test/CodeGen/X86/2011-12-15-vec_shift.ll @ 95:afa8332a0e37 LLVM3.8

LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 95c75e76d11b
children 803732b1fca8
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
10 ; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}} 10 ; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}}
11 ; CHECK-W-SSE4: psllw $2 11 ; CHECK-W-SSE4: psllw $2
12 12
13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector. 13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
14 ; CHECK-WO-SSE4: psllw $5, [[REG1:%xmm.]] 14 ; CHECK-WO-SSE4: psllw $5, [[REG1:%xmm.]]
15 ; CHECK-WO-SSE4: pand [[REG1]], [[REG2:%xmm.]] 15 ; CHECK-WO-SSE4: pxor [[REG2:%xmm.]], [[REG2:%xmm.]]
16 ; CHECK-WO-SSE4: pcmpeqb {{%xmm., }}[[REG2]] 16 ; CHECK-WO-SSE4: pcmpgtb {{%xmm., }}[[REG2]]
17 %1 = shl <16 x i8> %a, %b 17 %1 = shl <16 x i8> %a, %b
18 ret <16 x i8> %1 18 ret <16 x i8> %1
19 } 19 }