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comparison test/CodeGen/X86/SwizzleShuff.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 803732b1fca8
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
4 4
5 ; CHECK: pull_bitcast 5 ; CHECK: pull_bitcast
6 ; CHECK: xorl 6 ; CHECK: xorl
7 ; CHECK: ret 7 ; CHECK: ret
8 define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) { 8 define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
9 %A = load <4 x i8>* %pA 9 %A = load <4 x i8>, <4 x i8>* %pA
10 %B = load <4 x i8>* %pB 10 %B = load <4 x i8>, <4 x i8>* %pB
11 %C = xor <4 x i8> %A, %B 11 %C = xor <4 x i8> %A, %B
12 store <4 x i8> %C, <4 x i8>* %pA 12 store <4 x i8> %C, <4 x i8>* %pA
13 ret void 13 ret void
14 } 14 }
15 15
20 ; CHECK-NEXT: pshufd 20 ; CHECK-NEXT: pshufd
21 ; CHECK-NEXT: pshufd 21 ; CHECK-NEXT: pshufd
22 ; CHECK-NEXT: pxor 22 ; CHECK-NEXT: pxor
23 ; CHECK-NEXT: ret 23 ; CHECK-NEXT: ret
24 define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) { 24 define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
25 %A = load <4 x i32>* %pA 25 %A = load <4 x i32>, <4 x i32>* %pA
26 %B = load <4 x i32>* %pB 26 %B = load <4 x i32>, <4 x i32>* %pB
27 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6> 27 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
28 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2> 28 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
29 %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2> 29 %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
30 %R = xor <4 x i32> %S1, %S2 30 %R = xor <4 x i32> %S1, %S2
31 ret <4 x i32> %R 31 ret <4 x i32> %R
33 33
34 ; CHECK: pull_bitcast2 34 ; CHECK: pull_bitcast2
35 ; CHECK: xorl 35 ; CHECK: xorl
36 ; CHECK: ret 36 ; CHECK: ret
37 define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) { 37 define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
38 %A = load <4 x i8>* %pA 38 %A = load <4 x i8>, <4 x i8>* %pA
39 store <4 x i8> %A, <4 x i8>* %pC 39 store <4 x i8> %A, <4 x i8>* %pC
40 %B = load <4 x i8>* %pB 40 %B = load <4 x i8>, <4 x i8>* %pB
41 %C = xor <4 x i8> %A, %B 41 %C = xor <4 x i8> %A, %B
42 store <4 x i8> %C, <4 x i8>* %pA 42 store <4 x i8> %C, <4 x i8>* %pA
43 ret <4 x i8> %C 43 ret <4 x i8> %C
44 } 44 }
45 45
47 47
48 ; CHECK: reverse_1 48 ; CHECK: reverse_1
49 ; CHECK-NOT: pshufd 49 ; CHECK-NOT: pshufd
50 ; CHECK: ret 50 ; CHECK: ret
51 define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) { 51 define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
52 %A = load <4 x i32>* %pA 52 %A = load <4 x i32>, <4 x i32>* %pA
53 %B = load <4 x i32>* %pB 53 %B = load <4 x i32>, <4 x i32>* %pB
54 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 54 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
55 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 55 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
56 ret <4 x i32> %S1 56 ret <4 x i32> %S1
57 } 57 }
58 58
59 59
60 ; CHECK: no_reverse_shuff 60 ; CHECK: no_reverse_shuff
61 ; CHECK: pshufd 61 ; CHECK: pshufd
62 ; CHECK: ret 62 ; CHECK: ret
63 define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) { 63 define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
64 %A = load <4 x i32>* %pA 64 %A = load <4 x i32>, <4 x i32>* %pA
65 %B = load <4 x i32>* %pB 65 %B = load <4 x i32>, <4 x i32>* %pB
66 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 66 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
67 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2> 67 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
68 ret <4 x i32> %S1 68 ret <4 x i32> %S1
69 } 69 }