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comparison test/CodeGen/X86/function-subtarget-features.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents
children 803732b1fca8
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84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc < %s -march=x86-64 -o - | FileCheck %s
2
3 ; This test verifies that we produce different code for different architectures
4 ; based on target-cpu and target-features attributes.
5 ; In this case avx has a vmovss instruction and otherwise we should be using movss
6 ; to materialize constants.
7 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
8
9 define float @_Z3barv() #0 {
10 entry:
11 ret float 4.000000e+00
12 }
13
14 ; CHECK: barv
15 ; CHECK: vmovss
16
17 define float @_Z4testv() #1 {
18 entry:
19 ret float 1.000000e+00
20 }
21
22 ; CHECK: testv
23 ; CHECK: movss
24
25 define float @_Z3foov() #2 {
26 entry:
27 ret float 4.000000e+00
28 }
29
30 ; CHECK: foov
31 ; CHECK: movss
32
33 define float @_Z3bazv() #0 {
34 entry:
35 ret float 4.000000e+00
36 }
37
38 ; CHECK: bazv
39 ; CHECK: vmovss
40
41 define <2 x i64> @foo(<2 x i64> %a) #3 {
42 entry:
43 %a.addr = alloca <2 x i64>, align 16
44 store <2 x i64> %a, <2 x i64>* %a.addr, align 16
45 %0 = load <2 x i64>, <2 x i64>* %a.addr, align 16
46 %1 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %0, i8 4)
47 ret <2 x i64> %1
48 }
49
50 ; Function Attrs: nounwind readnone
51 declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8)
52
53 ; CHECK: foo
54 ; CHECK: aeskeygenassist
55
56 ; Function Attrs: nounwind uwtable
57 define i32 @bar(i32 %crc, i8* %a) #3 {
58 entry:
59 %crc.addr = alloca i32, align 4
60 %a.addr = alloca i8*, align 8
61 store i32 %crc, i32* %crc.addr, align 4
62 store i8* %a, i8** %a.addr, align 8
63 %0 = load i32, i32* %crc.addr, align 4
64 %1 = load i8*, i8** %a.addr, align 8
65 %incdec.ptr = getelementptr inbounds i8, i8* %1, i32 1
66 store i8* %incdec.ptr, i8** %a.addr, align 8
67 %2 = load i8, i8* %1, align 1
68 %3 = call i32 @llvm.x86.sse42.crc32.32.8(i32 %0, i8 %2)
69 ret i32 %3
70 }
71
72 ; Function Attrs: nounwind readnone
73 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8)
74
75 ; CHECK: bar
76 ; CHECK: crc32b
77
78 attributes #0 = { "target-cpu"="x86-64" "target-features"="+avx2" }
79 attributes #1 = { "target-cpu"="x86-64" }
80 attributes #2 = { "target-cpu"="corei7" "target-features"="+sse4.2" }
81 attributes #3 = { "target-cpu"="x86-64" "target-features"="+avx2,+aes" }