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comparison test/CodeGen/X86/sse3-avx-addsub.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
comparison
equal deleted inserted replaced
84:f3e34b893a5f 95:afa8332a0e37
85 ; AVX: vaddsubpd 85 ; AVX: vaddsubpd
86 ; CHECK-NEXT: ret 86 ; CHECK-NEXT: ret
87 87
88 88
89 define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) { 89 define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
90 %1 = load <4 x float>* %B 90 %1 = load <4 x float>, <4 x float>* %B
91 %add = fadd <4 x float> %A, %1 91 %add = fadd <4 x float> %A, %1
92 %sub = fsub <4 x float> %A, %1 92 %sub = fsub <4 x float> %A, %1
93 %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 93 %vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
94 ret <4 x float> %vecinit6 94 ret <4 x float> %vecinit6
95 } 95 }
98 ; AVX: vaddsubps 98 ; AVX: vaddsubps
99 ; CHECK-NEXT: ret 99 ; CHECK-NEXT: ret
100 100
101 101
102 define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) { 102 define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
103 %1 = load <8 x float>* %B 103 %1 = load <8 x float>, <8 x float>* %B
104 %add = fadd <8 x float> %A, %1 104 %add = fadd <8 x float> %A, %1
105 %sub = fsub <8 x float> %A, %1 105 %sub = fsub <8 x float> %A, %1
106 %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> 106 %vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
107 ret <8 x float> %vecinit14 107 ret <8 x float> %vecinit14
108 } 108 }
113 ; AVX-NOT: vaddsubps 113 ; AVX-NOT: vaddsubps
114 ; CHECK: ret 114 ; CHECK: ret
115 115
116 116
117 define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) { 117 define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
118 %1 = load <4 x double>* %B 118 %1 = load <4 x double>, <4 x double>* %B
119 %add = fadd <4 x double> %A, %1 119 %add = fadd <4 x double> %A, %1
120 %sub = fsub <4 x double> %A, %1 120 %sub = fsub <4 x double> %A, %1
121 %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 121 %vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
122 ret <4 x double> %vecinit6 122 ret <4 x double> %vecinit6
123 } 123 }
128 ; AVX-NOT: vaddsubpd 128 ; AVX-NOT: vaddsubpd
129 ; CHECK: ret 129 ; CHECK: ret
130 130
131 131
132 define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) { 132 define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
133 %1 = load <2 x double>* %B 133 %1 = load <2 x double>, <2 x double>* %B
134 %sub = fsub <2 x double> %A, %1 134 %sub = fsub <2 x double> %A, %1
135 %add = fadd <2 x double> %A, %1 135 %add = fadd <2 x double> %A, %1
136 %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3> 136 %vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
137 ret <2 x double> %vecinit2 137 ret <2 x double> %vecinit2
138 } 138 }