Mercurial > hg > CbC > CbC_llvm

comparison docs/AMDGPU/gfx10_hwreg.rst @ 147:c2174574ed3a

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents
children
comparison
equal deleted inserted replaced
134:3a76565eade5 147:c2174574ed3a
1 ..
2 **************************************************
3 * *
4 * Automatically generated file, do not edit! *
5 * *
6 **************************************************
7
8 .. _amdgpu_synid10_hwreg:
9
10 hwreg
11 ===========================
12
13 Bits of a hardware register being accessed.
14
15 The bits of this operand have the following meaning:
16
17 ============ ===================================
18 Bits Description
19 ============ ===================================
20 5:0 Register *id*.
21 10:6 First bit *offset* (0..31).
22 15:11 *Size* in bits (1..32).
23 ============ ===================================
24
25 This operand may be specified as a positive 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or using the syntax described below.
26
27 ==================================== ============================================================================
28 Syntax Description
29 ==================================== ============================================================================
30 hwreg({0..63}) All bits of a register indicated by its *id*.
31 hwreg(<*name*>) All bits of a register indicated by its *name*.
32 hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
33 hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
34 ==================================== ============================================================================
35
36 Register *id*, *offset* and *size* must be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`.
37
38 Defined register *names* include:
39
40 =================== ==========================================
41 Name Description
42 =================== ==========================================
43 HW_REG_MODE Shader writeable mode bits.
44 HW_REG_STATUS Shader read-only status.
45 HW_REG_TRAPSTS Trap status.
46 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
47 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
48 HW_REG_LDS_ALLOC Per-wave LDS allocation.
49 HW_REG_IB_STS Counters of outstanding instructions.
50 HW_REG_SH_MEM_BASES Memory aperture.
51 HW_REG_TBA_LO tba_lo register.
52 HW_REG_TBA_HI tba_hi register.
53 HW_REG_TMA_LO tma_lo register.
54 HW_REG_TMA_HI tma_hi register.
55 HW_REG_FLAT_SCR_LO flat_scratch_lo register.
56 HW_REG_FLAT_SCR_HI flat_scratch_hi register.
57 HW_REG_XNACK_MASK xnack_mask register.
58 HW_REG_POPS_PACKER pops_packer register.
59 =================== ==========================================
60
61 Examples:
62
63 .. parsed-literal::
64
65 s_getreg_b32 s2, 0x6
66 s_getreg_b32 s2, hwreg(15)
67 s_getreg_b32 s2, hwreg(51, 1, 31)
68 s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
69