CbC/CbC_llvm: lib/Target/Hexagon/HexagonExpandCondsets.cpp comparison

comparison lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 147:c2174574ed3a

LLVM 10

author	Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date	Wed, 14 Aug 2019 16:55:33 +0900
parents	3a76565eade5
children

comparison

equal deleted inserted replaced

-:3a76565eade5
+:c2174574ed3a
 //===- HexagonExpandCondsets.cpp ------------------------------------------===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 // Replace mux instructions with the corresponding legal instructions.
 // It is meant to work post-SSA, but still on virtual registers. It was
 }
 return false;
 }
 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
-assert(TargetRegisterInfo::isVirtualRegister(Reg));
+assert(Register::isVirtualRegister(Reg));
 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
 : MRI->getMaxLaneMaskForVReg(Reg);
 }
 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
 void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
 MachineInstr *MI = LIS->getInstructionFromIndex(K);
-for (auto &Op : MI->operands()) {
+for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
+MachineOperand &Op = MI->getOperand(i);
+if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
+MI->isRegTiedToDefOperand(i))
 continue;
 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
 if ((SLM & LM) == SLM) {
 // Only set the kill flag on the first encountered use of Reg in this
 // instruction.
 }
 }
 void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
 LiveRange &Range) {
-assert(TargetRegisterInfo::isVirtualRegister(Reg));
+assert(Register::isVirtualRegister(Reg));
 if (Range.empty())
 return;
 // Return two booleans: { def-modifes-reg, def-covers-reg }.
 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
 if (!Op.isReg() || !Op.isDef())
 return { false, false };
 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
-if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
+if (!Register::isVirtualRegister(DR) || DR != Reg)
 return { false, false };
 LaneBitmask SLM = getLaneMask(DR, DSR);
 LaneBitmask A = SLM & LM;
 return { A.any(), A == SLM };
 };
 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
 MachineOperand &Op = DefI->getOperand(i);
 if (!Op.isReg() || !DefRegs.count(Op))
 continue;
 if (Op.isDef()) {
-ImpUses.insert({Op, i});
+// Tied defs will always have corresponding uses, so no extra
+// implicit uses are needed.
+if (!Op.isTied())
+ImpUses.insert({Op, i});
 } else {
 // This function can be called for the same register with different
 // lane masks. If the def in this instruction was for the whole
 // register, we can get here more than once. Avoid adding multiple
 // implicit uses (or adding an implicit use when an explicit one is
 // present).
-ImpUses.erase(Op);
+if (Op.isTied())
+ImpUses.erase(Op);
 }
 }
 if (ImpUses.empty())
 continue;
 MachineFunction &MF = *DefI->getParent()->getParent();
 }
 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
 bool Recalc, bool UpdateKills, bool UpdateDeads) {
 UpdateKills |= UpdateDeads;
-for (auto R : RegSet) {
+for (unsigned R : RegSet) {
+if (!Register::isVirtualRegister(R)) {
+assert(Register::isPhysicalRegister(R));
+// There shouldn't be any physical registers as operands, except
+// possibly reserved registers.
+assert(MRI->isReserved(R));
+continue;
+}
 if (Recalc)
 recalculateLiveInterval(R);
 if (UpdateKills)
 MRI->clearKillFlags(R);
 if (UpdateDeads)
 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
 bool IfTrue) {
 using namespace Hexagon;
 if (SO.isReg()) {
-unsigned PhysR;
+Register PhysR;
 RegisterRef RS = SO;
-if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
+if (Register::isVirtualRegister(RS.Reg)) {
 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
 assert(VC->begin() != VC->end() && "Empty register class");
 PhysR = *VC->begin();
 } else {
-assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
+assert(Register::isPhysicalRegister(RS.Reg));
 PhysR = RS.Reg;
 }
 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
 switch (TRI->getRegSizeInBits(*RC)) {
 .addReg(DstR, DstState, DstSR)
 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
 .add(SrcOp);
 }
-DEBUG(dbgs() << "created an initial copy: " << *MIB);
+LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB);
 return &*MIB;
 }
 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
 /// performs all necessary changes to complete the replacement.
 if (TfrLimitActive) {
 if (TfrCounter >= TfrLimit)
 return false;
 TfrCounter++;
 }
-DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": "
+LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent())
-<< MI);
+<< ": " << MI);
 MachineOperand &MD = MI.getOperand(0);  // Definition
 MachineOperand &MP = MI.getOperand(1);  // Predicate register
 assert(MD.isDef());
 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
 bool ReadUndef = MD.isUndef();
 if (HasDef)
 return false;
 HasDef = true;
 }
 for (auto &Mo : MI->memoperands())
-if (Mo->isVolatile())
+if (Mo->isVolatile() || Mo->isAtomic())
 return false;
 return true;
 }
 /// Find the reaching definition for a predicated use of RD. The RD is used
 continue;
 RegisterRef RR = Op;
 // For physical register we would need to check register aliases, etc.
 // and we don't want to bother with that. It would be of little value
 // before the actual register rewriting (from virtual to physical).
-if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+if (!Register::isVirtualRegister(RR.Reg))
 return false;
 // No redefs for any operand.
 if (isRefInMap(RR, Defs, Exec_Then))
 return false;
 // For defs, there cannot be uses.
 MachineOperand &MO = MI.getOperand(Ox);
 if (!MO.isReg() || !MO.isImplicit())
 MB.add(MO);
 Ox++;
 }
+MB.cloneMemRefs(MI);
-MachineFunction &MF = *B.getParent();
-MachineInstr::mmo_iterator I = MI.memoperands_begin();
-unsigned NR = std::distance(I, MI.memoperands_end());
-MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
-for (unsigned i = 0; i < NR; ++i)
-MemRefs[i] = *I++;
-MB.setMemRefs(MemRefs, MemRefs+NR);
 MachineInstr *NewI = MB;
 NewI->clearKillInfo();
 LIS->InsertMachineInstrInMaps(*NewI);
 std::set<unsigned> &UpdRegs) {
 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
 unsigned Opc = TfrI.getOpcode();
 (void)Opc;
 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
-DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
+LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
 << ": " << TfrI);
 MachineOperand &MD = TfrI.getOperand(0);
 MachineOperand &MP = TfrI.getOperand(1);
 MachineOperand &MS = TfrI.getOperand(2);
 // The source operand should be a <kill>. This is not strictly necessary,
 unsigned PredR = MP.getReg();
 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
 if (!DefI || !isPredicable(DefI))
 return false;
-DEBUG(dbgs() << "Source def: " << *DefI);
+LLVM_DEBUG(dbgs() << "Source def: " << *DefI);
 // Collect the information about registers defined and used between the
 // DefI and the TfrI.
 // Map: reg -> bitmask of subregs
 ReferenceMap Uses, Defs;
 // in the subregisters, which we are keeping track of. Physical
 // registers ters no longer have subregisters---their super- and
 // subregisters are other physical registers, and we are not checking
 // that.
 RegisterRef RR = Op;
-if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+if (!Register::isVirtualRegister(RR.Reg))
 return false;
 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
 if (Op.isDef() && Op.isUndef()) {
 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
 // to move DefI down to TfrI.
 if (DefI->mayLoad() || DefI->mayStore())
 if (!canMoveMemTo(*DefI, TfrI, true))
 CanDown = false;
-DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
+LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
 << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
 MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
 if (CanUp)
 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
 else if (CanDown)
 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
 }
 return Changed;
 }
 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
-if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+if (!Register::isVirtualRegister(RR.Reg))
 return false;
 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
 if (RC == &Hexagon::IntRegsRegClass) {
 BW = 32;
 return true;
 return false;
 if (L1.hasSubRanges() || L2.hasSubRanges())
 return false;
 bool Overlap = L1.overlaps(L2);
-DEBUG(dbgs() << "compatible registers: ("
+LLVM_DEBUG(dbgs() << "compatible registers: ("
 << (Overlap ? "overlap" : "disjoint") << ")\n  "
 << printReg(R1.Reg, TRI, R1.Sub) << "  " << L1 << "\n  "
 << printReg(R2.Reg, TRI, R2.Sub) << "  " << L2 << "\n");
 if (R1.Sub || R2.Sub)
 return false;
 if (Overlap)
 return false;
 while (L2.begin() != L2.end())
 L2.removeSegment(*L2.begin());
 LIS->removeInterval(R2.Reg);
 updateKillFlags(R1.Reg);
-DEBUG(dbgs() << "coalesced: " << L1 << "\n");
+LLVM_DEBUG(dbgs() << "coalesced: " << L1 << "\n");
 L1.verify();
 return true;
 }
 TRI = MF.getSubtarget().getRegisterInfo();
 MDT = &getAnalysis<MachineDominatorTree>();
 LIS = &getAnalysis<LiveIntervals>();
 MRI = &MF.getRegInfo();
-DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
+LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
 MF.getFunction().getParent()));
 bool Changed = false;
 std::set<unsigned> CoalUpd, PredUpd;
 SmallVector<MachineInstr*,16> Condsets;
 for (MachineOperand &Op : MI->operands())
 if (Op.isReg() && Op.isUse())
 if (!CoalUpd.count(Op.getReg()))
 KillUpd.insert(Op.getReg());
 updateLiveness(KillUpd, false, true, false);
-DEBUG(LIS->print(dbgs() << "After coalescing\n",
+LLVM_DEBUG(
-MF.getFunction().getParent()));
+LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent()));
 // First, simply split all muxes into a pair of conditional transfers
 // and update the live intervals to reflect the new arrangement. The
 // goal is to update the kill flags, since predication will rely on
 // them.
 // intervals removes kill flags, which were preserved by splitting on
 // the source operands of condsets. These kill flags are needed by
 // predication, and after splitting they are difficult to recalculate
 // (because of predicated defs), so make sure they are left untouched.
 // Predication does not use live intervals.
-DEBUG(LIS->print(dbgs() << "After splitting\n",
+LLVM_DEBUG(
-MF.getFunction().getParent()));
+LIS->print(dbgs() << "After splitting\n", MF.getFunction().getParent()));
 // Traverse all blocks and collapse predicable instructions feeding
 // conditional transfers into predicated instructions.
 // Walk over all the instructions again, so we may catch pre-existing
 // cases that were not created in the previous step.
 for (auto &B : MF)
 Changed |= predicateInBlock(B, PredUpd);
-DEBUG(LIS->print(dbgs() << "After predicating\n",
+LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n",
 MF.getFunction().getParent()));
 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
 updateLiveness(PredUpd, true, true, true);
-DEBUG({
+LLVM_DEBUG({
 if (Changed)
 LIS->print(dbgs() << "After expand-condsets\n",
 MF.getFunction().getParent());
 });
 }
 //===----------------------------------------------------------------------===//
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 FunctionPass *llvm::createHexagonExpandCondsets() {
 return new HexagonExpandCondsets();
 }

Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 147:c2174574ed3a