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comparison lib/Target/Hexagon/HexagonVectorPrint.cpp @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 3a76565eade5
children
comparison
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134:3a76565eade5 147:c2174574ed3a
1 //===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===// 1 //===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // This pass adds the capability to generate pseudo vector/predicate register 9 // This pass adds the capability to generate pseudo vector/predicate register
11 // printing instructions. These pseudo instructions should be used with the 10 // printing instructions. These pseudo instructions should be used with the
142 if (MII->getNumOperands() < 1) 141 if (MII->getNumOperands() < 1)
143 continue; 142 continue;
144 unsigned Reg = 0; 143 unsigned Reg = 0;
145 if (getInstrVecReg(*MII, Reg)) { 144 if (getInstrVecReg(*MII, Reg)) {
146 VecPrintList.push_back((&*MII)); 145 VecPrintList.push_back((&*MII));
147 DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump()); 146 LLVM_DEBUG(dbgs() << "Found vector reg inside bundle \n";
147 MII->dump());
148 } 148 }
149 } 149 }
150 } else { 150 } else {
151 unsigned Reg = 0; 151 unsigned Reg = 0;
152 if (getInstrVecReg(MI, Reg)) { 152 if (getInstrVecReg(MI, Reg)) {
153 VecPrintList.push_back(&MI); 153 VecPrintList.push_back(&MI);
154 DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); 154 LLVM_DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
155 } 155 }
156 } 156 }
157 } 157 }
158 158
159 Changed = !VecPrintList.empty(); 159 Changed = !VecPrintList.empty();
161 return Changed; 161 return Changed;
162 162
163 for (auto *I : VecPrintList) { 163 for (auto *I : VecPrintList) {
164 DebugLoc DL = I->getDebugLoc(); 164 DebugLoc DL = I->getDebugLoc();
165 MachineBasicBlock *MBB = I->getParent(); 165 MachineBasicBlock *MBB = I->getParent();
166 DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); 166 LLVM_DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
167 unsigned Reg = 0; 167 unsigned Reg = 0;
168 if (!getInstrVecReg(*I, Reg)) 168 if (!getInstrVecReg(*I, Reg))
169 llvm_unreachable("Need a vector reg"); 169 llvm_unreachable("Need a vector reg");
170 MachineBasicBlock::instr_iterator MII = I->getIterator(); 170 MachineBasicBlock::instr_iterator MII = I->getIterator();
171 if (I->isInsideBundle()) { 171 if (I->isInsideBundle()) {
172 DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); 172 LLVM_DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
173 while (MBB->instr_end() != MII && MII->isInsideBundle()) 173 while (MBB->instr_end() != MII && MII->isInsideBundle())
174 MII++; 174 MII++;
175 } else { 175 } else {
176 DEBUG(dbgs() << "add after instruction\n"; I->dump()); 176 LLVM_DEBUG(dbgs() << "add after instruction\n"; I->dump());
177 MII++; 177 MII++;
178 } 178 }
179 if (MBB->instr_end() == MII) 179 if (MBB->instr_end() == MII)
180 continue; 180 continue;
181 181
182 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { 182 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
183 DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n'); 183 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');
184 addAsmInstr(MBB, Reg, MII, DL, QII, Fn); 184 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
185 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { 185 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
186 DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n'); 186 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n');
187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, 187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
188 MII, DL, QII, Fn); 188 MII, DL, QII, Fn);
189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, 189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
190 MII, DL, QII, Fn); 190 MII, DL, QII, Fn);
191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { 191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
192 DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n'); 192 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n');
193 addAsmInstr(MBB, Reg, MII, DL, QII, Fn); 193 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
194 } else 194 } else
195 llvm_unreachable("Bad Vector reg"); 195 llvm_unreachable("Bad Vector reg");
196 } 196 }
197 return Changed; 197 return Changed;