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comparison lib/Target/Mips/MipsInstrFPU.td @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 3a76565eade5
children
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134:3a76565eade5 147:c2174574ed3a
1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 // 8 //
10 // This file describes the Mips FPU instruction set. 9 // This file describes the Mips FPU instruction set.
11 // 10 //
128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 127 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
130 HARDFLOAT, 129 HARDFLOAT,
131 NeverHasSideEffects; 130 NeverHasSideEffects;
132 131
132 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm,
133 SDPatternOperator OpNode= null_frag> :
134 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
135 !strconcat(opstr, "\t$fd, $fs, $ft"),
136 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
137 HARDFLOAT {
138 let isCommutable = IsComm;
139 }
140
133 multiclass ABSS_M<string opstr, InstrItinClass Itin, 141 multiclass ABSS_M<string opstr, InstrItinClass Itin,
134 SDPatternOperator OpNode= null_frag> { 142 SDPatternOperator OpNode= null_frag> {
135 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 143 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
136 FGR_32; 144 FGR_32;
137 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { 145 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
138 string DecoderNamespace = "MipsFP64"; 146 string DecoderNamespace = "MipsFP64";
139 } 147 }
140 } 148 }
141 149
142 multiclass ROUND_M<string opstr, InstrItinClass Itin> { 150 multiclass ROUND_M<string opstr, InstrItinClass Itin> {
147 } 155 }
148 156
149 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 157 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 158 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 159 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT; 160 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
161 let isMoveReg = 1;
162 }
153 163
154 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 164 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
155 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 165 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
156 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 166 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
157 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT; 167 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
168 let isMoveReg = 1;
169 }
158 170
159 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 171 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
160 InstrItinClass Itin> : 172 InstrItinClass Itin> :
161 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 173 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
162 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 174 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
347 FGR_64; 359 FGR_64;
348 } 360 }
349 //===----------------------------------------------------------------------===// 361 //===----------------------------------------------------------------------===//
350 // Floating Point Instructions 362 // Floating Point Instructions
351 //===----------------------------------------------------------------------===// 363 //===----------------------------------------------------------------------===//
352 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 364 let AdditionalPredicates = [NotInMicroMips] in {
353 ABSS_FM<0xc, 16>, ISA_MIPS2; 365 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
354 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 366 ABSS_FM<0xc, 16>, ISA_MIPS2;
355 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 367 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
356 ABSS_FM<0xd, 16>, ISA_MIPS2; 368 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
357 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 369 ABSS_FM<0xd, 16>, ISA_MIPS2;
358 ABSS_FM<0xe, 16>, ISA_MIPS2; 370 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
359 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 371 ABSS_FM<0xe, 16>, ISA_MIPS2;
360 ABSS_FM<0xf, 16>, ISA_MIPS2; 372 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
361 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 373 ABSS_FM<0xf, 16>, ISA_MIPS2;
362 ABSS_FM<0x24, 16>; 374 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
363 375 ABSS_FM<0x24, 16>, ISA_MIPS1;
364 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 376
365 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 377 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
366 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 378 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
367 let AdditionalPredicates = [NotInMicroMips] in { 379 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
368 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; 380 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;
369 } 381 }
370 382
371 let AdditionalPredicates = [NotInMicroMips] in { 383 let AdditionalPredicates = [NotInMicroMips] in {
372 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 384 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
373 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 385 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
391 INSN_MIPS4_32R2, FGR_64; 403 INSN_MIPS4_32R2, FGR_64;
392 } 404 }
393 let DecoderNamespace = "MipsFP64" in { 405 let DecoderNamespace = "MipsFP64" in {
394 let AdditionalPredicates = [NotInMicroMips] in { 406 let AdditionalPredicates = [NotInMicroMips] in {
395 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 407 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
396 ABSS_FM<0x8, 16>, FGR_64; 408 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64;
397 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 409 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
398 ABSS_FM<0x8, 17>, FGR_64; 410 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64;
399 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 411 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
400 ABSS_FM<0x9, 16>, FGR_64; 412 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64;
401 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 413 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
402 ABSS_FM<0x9, 17>, FGR_64; 414 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64;
403 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 415 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
404 ABSS_FM<0xa, 16>, FGR_64; 416 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64;
405 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 417 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
406 ABSS_FM<0xa, 17>, FGR_64; 418 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64;
407 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 419 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
408 ABSS_FM<0xb, 16>, FGR_64; 420 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64;
409 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 421 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
410 ABSS_FM<0xb, 17>, FGR_64; 422 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64;
411 } 423 }
412 } 424 }
413 425
414 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
415 ABSS_FM<0x20, 20>;
416 let AdditionalPredicates = [NotInMicroMips] in{ 426 let AdditionalPredicates = [NotInMicroMips] in{
427 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
428 ABSS_FM<0x20, 20>, ISA_MIPS1;
417 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 429 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
418 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 430 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
419 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 431 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
420 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 432 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
421 } 433 }
422 434
423 let AdditionalPredicates = [NotInMicroMips] in { 435 let AdditionalPredicates = [NotInMicroMips] in {
424 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 436 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
425 ABSS_FM<0x20, 17>, FGR_32; 437 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
426 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 438 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
427 ABSS_FM<0x21, 16>, FGR_32; 439 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
428 } 440 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
429 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 441 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
430 ABSS_FM<0x21, 20>, FGR_32; 442 }
443
444 let DecoderNamespace = "MipsFP64" in {
445 let AdditionalPredicates = [NotInMicroMips] in {
446 def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
447 ADDS_FM<0x2C, 22>,
448 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
449 def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
450 ADDS_FM<0x2D, 22>,
451 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
452
453 def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
454 ABSS_FM<0x20, 22>,
455 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
456 def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,
457 ABSS_FM<0x28, 22>,
458 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
459
460 def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,
461 ADDS_FM<0x26, 16>,
462 ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
463 }
464 }
431 465
432 let DecoderNamespace = "MipsFP64" in { 466 let DecoderNamespace = "MipsFP64" in {
433 let AdditionalPredicates = [NotInMicroMips] in { 467 let AdditionalPredicates = [NotInMicroMips] in {
434 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 468 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
435 ABSS_FM<0x20, 21>, FGR_64; 469 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
436 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 470 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
437 ABSS_FM<0x20, 17>, FGR_64; 471 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
438 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 472 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
439 ABSS_FM<0x21, 20>, FGR_64; 473 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
440 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 474 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
441 ABSS_FM<0x21, 16>, FGR_64; 475 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
442 } 476 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
443 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 477 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;
444 ABSS_FM<0x21, 21>, FGR_64; 478 }
445 } 479 }
446 480
447 let isPseudo = 1, isCodeGenOnly = 1 in { 481 let isPseudo = 1, isCodeGenOnly = 1 in {
448 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 482 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
449 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 483 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
450 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 484 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
451 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 485 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
452 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 486 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
453 } 487 }
454 488
455 let AdditionalPredicates = [NotInMicroMips] in { 489 let AdditionalPredicates = [NotInMicroMips, UseAbs] in {
456 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 490 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
457 ABSS_FM<0x5, 16>; 491 ABSS_FM<0x5, 16>, ISA_MIPS1;
458 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; 492 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
459 } 493 }
460 494
461 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 495 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
462 ABSS_FM<0x7, 16>; 496 ABSS_FM<0x7, 16>, ISA_MIPS1;
463 let AdditionalPredicates = [NotInMicroMips] in { 497 let AdditionalPredicates = [NotInMicroMips] in {
464 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; 498 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
465 } 499 }
466 500
467 let AdditionalPredicates = [NotInMicroMips] in { 501 let AdditionalPredicates = [NotInMicroMips] in {
468 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 502 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
469 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 503 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
475 // When defining instructions, we reference all 32-bit registers, 509 // When defining instructions, we reference all 32-bit registers,
476 // regardless of register aliasing. 510 // regardless of register aliasing.
477 511
478 /// Move Control Registers From/To CPU Registers 512 /// Move Control Registers From/To CPU Registers
479 let AdditionalPredicates = [NotInMicroMips] in { 513 let AdditionalPredicates = [NotInMicroMips] in {
480 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; 514 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>,
481 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; 515 ISA_MIPS1;
482 } 516 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,
483 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 517 ISA_MIPS1;
484 bitconvert>, MFC1_FM<0>; 518
485 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 519 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
486 FGR_64 { 520 bitconvert>, MFC1_FM<0>, ISA_MIPS1;
487 let DecoderNamespace = "MipsFP64"; 521 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
488 } 522 ISA_MIPS1, FGR_64 {
489 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 523 let DecoderNamespace = "MipsFP64";
490 bitconvert>, MFC1_FM<4>; 524 }
491 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 525 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
492 FGR_64 { 526 bitconvert>, MFC1_FM<4>, ISA_MIPS1;
493 let DecoderNamespace = "MipsFP64"; 527 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
494 } 528 ISA_MIPS1, FGR_64 {
495 529 let DecoderNamespace = "MipsFP64";
496 let AdditionalPredicates = [NotInMicroMips] in { 530 }
531
497 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 532 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
498 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 533 MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
499 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 534 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
500 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 535 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
501 let DecoderNamespace = "MipsFP64"; 536 let DecoderNamespace = "MipsFP64";
502 } 537 }
503 } 538
504 let AdditionalPredicates = [NotInMicroMips] in {
505 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 539 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
506 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 540 MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
507 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 541 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
508 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 542 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
509 let DecoderNamespace = "MipsFP64"; 543 let DecoderNamespace = "MipsFP64";
510 } 544 }
511 } 545
512 let AdditionalPredicates = [NotInMicroMips] in {
513 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 546 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
514 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 547 bitconvert>, MFC1_FM<5>, ISA_MIPS3;
515 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 548 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
516 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 549 bitconvert>, MFC1_FM<1>, ISA_MIPS3;
517 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 550 let isMoveReg = 1 in {
518 ABSS_FM<0x6, 16>; 551 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
519 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 552 ABSS_FM<0x6, 16>, ISA_MIPS1;
520 ABSS_FM<0x6, 17>, FGR_32; 553 defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
521 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 554 } // isMoveReg
522 ABSS_FM<0x6, 17>, FGR_64 {
523 let DecoderNamespace = "MipsFP64";
524 }
525 } 555 }
526 556
527 /// Floating Point Memory Instructions 557 /// Floating Point Memory Instructions
528 let AdditionalPredicates = [NotInMicroMips] in { 558 let AdditionalPredicates = [NotInMicroMips] in {
529 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 559 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
530 LW_FM<0x31>; 560 LW_FM<0x31>, ISA_MIPS1;
531 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 561 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
532 LW_FM<0x39>; 562 LW_FM<0x39>, ISA_MIPS1;
533 } 563 }
534 564
535 let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 565 let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
536 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 566 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
537 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 567 LW_FM<0x35>, ISA_MIPS2, FGR_64 {
574 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 604 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
575 } 605 }
576 606
577 // Load/store doubleword indexed unaligned. 607 // Load/store doubleword indexed unaligned.
578 // FIXME: This instruction should not be defined for FGR_32. 608 // FIXME: This instruction should not be defined for FGR_32.
579 let AdditionalPredicates = [IsNotNaCl] in { 609 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
580 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 610 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
581 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 611 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
582 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 612 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
583 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 613 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
584 } 614 }
585 615
586 let DecoderNamespace="MipsFP64" in { 616 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
617 DecoderNamespace="MipsFP64" in {
587 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 618 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
588 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 619 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
589 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 620 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
590 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 621 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
591 } 622 }
592 623
593 /// Floating-point Aritmetic 624 /// Floating-point Aritmetic
594 let AdditionalPredicates = [NotInMicroMips] in { 625 let AdditionalPredicates = [NotInMicroMips] in {
595 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 626 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
596 ADDS_FM<0x00, 16>; 627 ADDS_FM<0x00, 16>, ISA_MIPS1;
597 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; 628 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>,
629 ISA_MIPS1;
598 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 630 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
599 ADDS_FM<0x03, 16>; 631 ADDS_FM<0x03, 16>, ISA_MIPS1;
600 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; 632 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
633 ISA_MIPS1;
601 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 634 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
602 ADDS_FM<0x02, 16>; 635 ADDS_FM<0x02, 16>, ISA_MIPS1;
603 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; 636 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>,
637 ISA_MIPS1;
604 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 638 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
605 ADDS_FM<0x01, 16>; 639 ADDS_FM<0x01, 16>, ISA_MIPS1;
606 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; 640 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>,
607 } 641 ISA_MIPS1;
608 642 }
609 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 643
610 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; 644 let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
611 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 645 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
612 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; 646 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
613 647 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
614 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { 648 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
649
650 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
651 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
652 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
653 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
654
655 let DecoderNamespace = "MipsFP64" in {
656 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
657 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
658 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
659 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
660 }
661 }
662
663 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
615 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 664 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
616 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 665 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
617 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 666 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
618 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 667 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
619 } 668
620
621 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
622 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
623 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
624 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
625
626 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
627 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 669 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
628 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 670 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
629 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 671 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
630 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 672 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
631 } 673
632 674 let DecoderNamespace = "MipsFP64" in {
633 let DecoderNamespace = "MipsFP64" in { 675 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
634 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 676 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
635 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; 677 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
636 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 678 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
637 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; 679 }
638 } 680 }
639
640 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
641 DecoderNamespace = "MipsFP64" in {
642 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
643 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
644 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
645 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
646 }
647
648 //===----------------------------------------------------------------------===// 681 //===----------------------------------------------------------------------===//
649 // Floating Point Branch Codes 682 // Floating Point Branch Codes
650 //===----------------------------------------------------------------------===// 683 //===----------------------------------------------------------------------===//
651 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 684 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
652 // They must be kept in synch. 685 // They must be kept in synch.
752 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 785 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),
753 (ins imm64:$fpimm), 786 (ins imm64:$fpimm),
754 "li.d\t$rd, $fpimm">, 787 "li.d\t$rd, $fpimm">,
755 FGR_64, HARDFLOAT; 788 FGR_64, HARDFLOAT;
756 789
790 def SDC1_M1 : MipsAsmPseudoInst<(outs AFGR64Opnd:$fd),
791 (ins mem_simm16:$addr),
792 "s.d\t$fd, $addr">,
793 FGR_32, ISA_MIPS1, HARDFLOAT;
794
757 //===----------------------------------------------------------------------===// 795 //===----------------------------------------------------------------------===//
758 // InstAliases. 796 // InstAliases.
759 //===----------------------------------------------------------------------===// 797 //===----------------------------------------------------------------------===//
760 def : MipsInstAlias 798 def : MipsInstAlias
761 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 799 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
764 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 802 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
765 FGR_32, ISA_MIPS2, HARDFLOAT; 803 FGR_32, ISA_MIPS2, HARDFLOAT;
766 def : MipsInstAlias 804 def : MipsInstAlias
767 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 805 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>,
768 FGR_64, ISA_MIPS2, HARDFLOAT; 806 FGR_64, ISA_MIPS2, HARDFLOAT;
807 def : MipsInstAlias
808 <"s.d $fd, $addr", (SDC1_M1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
809 FGR_32, ISA_MIPS1, HARDFLOAT;
769 810
770 def : MipsInstAlias 811 def : MipsInstAlias
771 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 812 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>,
772 ISA_MIPS2, HARDFLOAT; 813 ISA_MIPS2, HARDFLOAT;
773 def : MipsInstAlias 814 def : MipsInstAlias
851 HARDFLOAT; 892 HARDFLOAT;
852 } 893 }
853 //===----------------------------------------------------------------------===// 894 //===----------------------------------------------------------------------===//
854 // Floating Point Patterns 895 // Floating Point Patterns
855 //===----------------------------------------------------------------------===// 896 //===----------------------------------------------------------------------===//
856 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 897 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
857 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 898 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
858 899
859 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 900 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
860 (PseudoCVT_S_W GPR32Opnd:$src)>; 901 (PseudoCVT_S_W GPR32Opnd:$src)>;
861 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 902 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
862 (TRUNC_W_S FGR32Opnd:$src)>; 903 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1;
863 904
864 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 905 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
865 (MTC1_D64 GPR32Opnd:$src)>, FGR_64; 906 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
866 907
867 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 908 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
868 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 909 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
869 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 910 let AdditionalPredicates = [NotInMicroMips] in {
870 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; 911 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
871 let AdditionalPredicates = [NotInMicroMips] in { 912 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32;
872 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 913 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
873 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; 914 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32;
874 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 915 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
875 (CVT_D32_S FGR32Opnd:$src)>, FGR_32; 916 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32;
876 } 917 }
877 918
878 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; 919 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
879 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; 920 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
921 FGR_64;
880 922
881 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 923 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
882 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 924 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
883 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 925 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
884 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 926 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
885 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 927 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
886 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 928 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
887 929
888 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 930 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
889 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; 931 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;
890 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 932 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
891 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64; 933 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64;
892 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 934 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
893 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; 935 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64;
894 936
895 let AdditionalPredicates = [NotInMicroMips] in { 937 let AdditionalPredicates = [NotInMicroMips] in {
896 def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 938 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
897 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; 939 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64;
898 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 940 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)),
899 (CVT_D64_S FGR32Opnd:$src)>, FGR_64; 941 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64;
900 } 942 }
901 943
902 // To generate NMADD and NMSUB instructions when fneg node is present 944 // To generate NMADD and NMSUB instructions when fneg node is present
903 multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 945 multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> {
904 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 946 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)),
914 } 956 }
915 957
916 // Patterns for loads/stores with a reg+imm operand. 958 // Patterns for loads/stores with a reg+imm operand.
917 let AdditionalPredicates = [NotInMicroMips] in { 959 let AdditionalPredicates = [NotInMicroMips] in {
918 let AddedComplexity = 40 in { 960 let AddedComplexity = 40 in {
919 def : LoadRegImmPat<LWC1, f32, load>; 961 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1;
920 def : StoreRegImmPat<SWC1, f32>; 962 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1;
921 963
922 def : LoadRegImmPat<LDC164, f64, load>, FGR_64; 964 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64;
923 def : StoreRegImmPat<SDC164, f64>, FGR_64; 965 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64;
924 966
925 def : LoadRegImmPat<LDC1, f64, load>, FGR_32; 967 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32;
926 def : StoreRegImmPat<SDC1, f64>, FGR_32; 968 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32;
927 } 969 }
928 } 970 }