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comparison lib/Target/PowerPC/PPCScheduleA2.td @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 1172e4bd9c6f
children
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134:3a76565eade5 147:c2174574ed3a
1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===// 1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 8
10 // Primary reference: 9 // Primary reference:
11 // A2 Processor User's Manual. 10 // A2 Processor User's Manual.
79 [6, 0, 0]>, 78 [6, 0, 0]>,
80 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>], 79 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
81 [6, 0, 0]>, 80 [6, 0, 0]>,
82 InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>], 81 InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
83 [0, 0, 0]>, 82 [0, 0, 0]>,
84 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
85 [2, 0, 0, 0]>,
86 InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>], 83 InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
87 [16, 0, 0]>, 84 [16, 0, 0]>,
88 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>], 85 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
89 [0, 0, 0]>, 86 [0, 0, 0]>,
90 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>], 87 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
103 [6, 8, 0, 0]>, 100 [6, 8, 0, 0]>,
104 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>], 101 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
105 [82, 0, 0]>, // L2 latency 102 [82, 0, 0]>, // L2 latency
106 InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>], 103 InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
107 [0, 0, 0]>, 104 [0, 0, 0]>,
108 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>], 105 InstrItinData<IIC_LdStSTU, [InstrStage<1, [A2_XU]>],
109 [2, 0, 0, 0]>, 106 [2, 0, 0, 0]>,
110 InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>], 107 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [A2_XU]>],
111 [2, 0, 0, 0]>, 108 [2, 0, 0, 0]>,
112 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>], 109 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
113 [82, 0, 0]>, // L2 latency 110 [82, 0, 0]>, // L2 latency
114 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>], 111 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
115 [82, 0, 0]>, // L2 latency 112 [82, 0, 0]>, // L2 latency