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comparison test/CodeGen/AArch64/fast-isel-sdiv.ll @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents afa8332a0e37
children
comparison
equal deleted inserted replaced
134:3a76565eade5 147:c2174574ed3a
1 ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s 2 ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ISEL
3 ; RUN: llc -mtriple=aarch64-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,FAST
3 4
4 define i32 @sdiv_i32_exact(i32 %a) { 5 define i32 @sdiv_i32_exact(i32 %a) {
5 ; CHECK-LABEL: sdiv_i32_exact 6 ; CHECK-LABEL: sdiv_i32_exact:
6 ; CHECK: asr {{w[0-9]+}}, w0, #3 7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: asr w0, w0, #3
9 ; CHECK-NEXT: ret
7 %1 = sdiv exact i32 %a, 8 10 %1 = sdiv exact i32 %a, 8
8 ret i32 %1 11 ret i32 %1
9 } 12 }
10 13
11 define i32 @sdiv_i32_pos(i32 %a) { 14 define i32 @sdiv_i32_pos(i32 %a) {
12 ; CHECK-LABEL: sdiv_i32_pos 15 ; CHECK-LABEL: sdiv_i32_pos:
13 ; CHECK: add [[REG1:w[0-9]+]], w0, #7 16 ; CHECK: // %bb.0:
14 ; CHECK-NEXT: cmp w0, #0 17 ; CHECK-NEXT: add w8, w0, #7 // =7
15 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt 18 ; CHECK-NEXT: cmp w0, #0 // =0
16 ; CHECK-NEXT: asr {{w[0-9]+}}, [[REG2]], #3 19 ; CHECK-NEXT: csel w8, w8, w0, lt
20 ; CHECK-NEXT: asr w0, w8, #3
21 ; CHECK-NEXT: ret
17 %1 = sdiv i32 %a, 8 22 %1 = sdiv i32 %a, 8
18 ret i32 %1 23 ret i32 %1
19 } 24 }
20 25
21 define i32 @sdiv_i32_neg(i32 %a) { 26 define i32 @sdiv_i32_neg(i32 %a) {
22 ; CHECK-LABEL: sdiv_i32_neg 27 ; CHECK-LABEL: sdiv_i32_neg:
23 ; CHECK: add [[REG1:w[0-9]+]], w0, #7 28 ; CHECK: // %bb.0:
24 ; CHECK-NEXT: cmp w0, #0 29 ; CHECK-NEXT: add w8, w0, #7 // =7
25 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt 30 ; CHECK-NEXT: cmp w0, #0 // =0
26 ; CHECK-NEXT: neg {{w[0-9]+}}, [[REG2]], asr #3 31 ; CHECK-NEXT: csel w8, w8, w0, lt
32 ; CHECK-NEXT: neg w0, w8, asr #3
33 ; CHECK-NEXT: ret
27 %1 = sdiv i32 %a, -8 34 %1 = sdiv i32 %a, -8
28 ret i32 %1 35 ret i32 %1
29 } 36 }
30 37
31 define i64 @sdiv_i64_exact(i64 %a) { 38 define i64 @sdiv_i64_exact(i64 %a) {
32 ; CHECK-LABEL: sdiv_i64_exact 39 ; CHECK-LABEL: sdiv_i64_exact:
33 ; CHECK: asr {{x[0-9]+}}, x0, #4 40 ; CHECK: // %bb.0:
41 ; CHECK-NEXT: asr x0, x0, #4
42 ; CHECK-NEXT: ret
34 %1 = sdiv exact i64 %a, 16 43 %1 = sdiv exact i64 %a, 16
35 ret i64 %1 44 ret i64 %1
36 } 45 }
37 46
38 define i64 @sdiv_i64_pos(i64 %a) { 47 define i64 @sdiv_i64_pos(i64 %a) {
39 ; CHECK-LABEL: sdiv_i64_pos 48 ; CHECK-LABEL: sdiv_i64_pos:
40 ; CHECK: add [[REG1:x[0-9]+]], x0, #15 49 ; CHECK: // %bb.0:
41 ; CHECK-NEXT: cmp x0, #0 50 ; CHECK-NEXT: add x8, x0, #15 // =15
42 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt 51 ; CHECK-NEXT: cmp x0, #0 // =0
43 ; CHECK-NEXT: asr {{x[0-9]+}}, [[REG2]], #4 52 ; CHECK-NEXT: csel x8, x8, x0, lt
53 ; CHECK-NEXT: asr x0, x8, #4
54 ; CHECK-NEXT: ret
44 %1 = sdiv i64 %a, 16 55 %1 = sdiv i64 %a, 16
45 ret i64 %1 56 ret i64 %1
46 } 57 }
47 58
48 define i64 @sdiv_i64_neg(i64 %a) { 59 define i64 @sdiv_i64_neg(i64 %a) {
49 ; CHECK-LABEL: sdiv_i64_neg 60 ; CHECK-LABEL: sdiv_i64_neg:
50 ; CHECK: add [[REG1:x[0-9]+]], x0, #15 61 ; CHECK: // %bb.0:
51 ; CHECK-NEXT: cmp x0, #0 62 ; CHECK-NEXT: add x8, x0, #15 // =15
52 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt 63 ; CHECK-NEXT: cmp x0, #0 // =0
53 ; CHECK-NEXT: neg {{x[0-9]+}}, [[REG2]], asr #4 64 ; CHECK-NEXT: csel x8, x8, x0, lt
65 ; CHECK-NEXT: neg x0, x8, asr #4
66 ; CHECK-NEXT: ret
54 %1 = sdiv i64 %a, -16 67 %1 = sdiv i64 %a, -16
55 ret i64 %1 68 ret i64 %1
56 } 69 }