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comparison utils/TableGen/DisassemblerEmitter.cpp @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 803732b1fca8
children
comparison
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134:3a76565eade5 147:c2174574ed3a
1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // 4 // See https://llvm.org/LICENSE.txt for license information.
5 // This file is distributed under the University of Illinois Open Source 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 // License. See LICENSE.TXT for details.
7 // 6 //
8 //===----------------------------------------------------------------------===// 7 //===----------------------------------------------------------------------===//
9 8
10 #include "CodeGenTarget.h" 9 #include "CodeGenTarget.h"
10 #include "WebAssemblyDisassemblerEmitter.h"
11 #include "X86DisassemblerTables.h" 11 #include "X86DisassemblerTables.h"
12 #include "X86RecognizableInstr.h" 12 #include "X86RecognizableInstr.h"
13 #include "llvm/TableGen/Error.h" 13 #include "llvm/TableGen/Error.h"
14 #include "llvm/TableGen/Record.h" 14 #include "llvm/TableGen/Record.h"
15 #include "llvm/TableGen/TableGenBackend.h" 15 #include "llvm/TableGen/TableGenBackend.h"
72 /// problem. 72 /// problem.
73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
74 /// accurate. Sometimes they are not. 74 /// accurate. Sometimes they are not.
75 /// (3) to fix the tables to reflect the actual context (for example, required 75 /// (3) to fix the tables to reflect the actual context (for example, required
76 /// prefixes), and possibly to add a new context by editing 76 /// prefixes), and possibly to add a new context by editing
77 /// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be 77 /// include/llvm/Support/X86DisassemblerDecoderCommon.h. This is unlikely
78 /// the cause. 78 /// to be the cause.
79 /// 79 ///
80 /// DisassemblerEmitter.cpp contains the implementation for the emitter, 80 /// DisassemblerEmitter.cpp contains the implementation for the emitter,
81 /// which simply pulls out instructions from the CodeGenTarget and pushes them 81 /// which simply pulls out instructions from the CodeGenTarget and pushes them
82 /// into X86DisassemblerTables. 82 /// into X86DisassemblerTables.
83 /// X86DisassemblerTables.h contains the interface for the instruction tables, 83 /// X86DisassemblerTables.h contains the interface for the instruction tables,
123 123
124 Tables.emit(OS); 124 Tables.emit(OS);
125 return; 125 return;
126 } 126 }
127 127
128 // WebAssembly has variable length opcodes, so can't use EmitFixedLenDecoder
129 // below (which depends on a Size table-gen Record), and also uses a custom
130 // disassembler.
131 if (Target.getName() == "WebAssembly") {
132 emitWebAssemblyDisassemblerTables(OS, Target.getInstructionsByEnumValue());
133 return;
134 }
135
128 // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. 136 // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
129 if (Target.getName() == "ARM" || Target.getName() == "Thumb" || 137 if (Target.getName() == "ARM" || Target.getName() == "Thumb" ||
130 Target.getName() == "AArch64" || Target.getName() == "ARM64") { 138 Target.getName() == "AArch64" || Target.getName() == "ARM64") {
131 std::string PredicateNamespace = Target.getName(); 139 std::string PredicateNamespace = Target.getName();
132 if (PredicateNamespace == "Thumb") 140 if (PredicateNamespace == "Thumb")