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comparison llvm/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll @ 236:c4bab56944e8 llvm-original

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LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 79ff65ed7e25
children 1f2b6ac9f198
comparison
equal deleted inserted replaced
232:70dce7da266c 236:c4bab56944e8
8 ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll 8 ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll
9 ; to avoid gfx9 scheduling induced issues. 9 ; to avoid gfx9 scheduling induced issues.
10 10
11 11
12 ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block: 12 ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block:
13 ; GCN-DAG: s_load_dwordx16 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]{{\]}} 13 ; GCN-DAG: s_load_dwordx16 s[[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]]
14 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]] 14 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]]
15 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62 15 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
16 16
17 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]] 17 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
18 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]] 18 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]