Mercurial > hg > CbC > CbC_llvm

comparison llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir @ 236:c4bab56944e8 llvm-original

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 79ff65ed7e25
children 1f2b6ac9f198
comparison
equal deleted inserted replaced
232:70dce7da266c 236:c4bab56944e8
9 S_NOP 0, implicit $vgpr1_vgpr2 9 S_NOP 0, implicit $vgpr1_vgpr2
10 %0:vreg_64 = IMPLICIT_DEF 10 %0:vreg_64 = IMPLICIT_DEF
11 S_NOP 0, implicit %0 11 S_NOP 0, implicit %0
12 12
13 %1:sreg_64_xexec = IMPLICIT_DEF 13 %1:sreg_64_xexec = IMPLICIT_DEF
14 %2:sreg_64_xexec = SI_CALL %1, 0, csr_amdgpu_highregs, implicit $vgpr1_vgpr2 14 %2:sreg_64_xexec = SI_CALL %1, 0, csr_amdgpu, implicit $vgpr1_vgpr2
15 15
16 ; noreg is OK 16 ; noreg is OK
17 DS_WRITE_B64_gfx9 $noreg, $noreg, 0, 0, implicit $exec 17 DS_WRITE_B64_gfx9 $noreg, $noreg, 0, 0, implicit $exec
18 ... 18 ...
19 19
107 %9:vgpr_32 = IMPLICIT_DEF 107 %9:vgpr_32 = IMPLICIT_DEF
108 %10:areg_64 = IMPLICIT_DEF 108 %10:areg_64 = IMPLICIT_DEF
109 %11:areg_128_align2 = IMPLICIT_DEF 109 %11:areg_128_align2 = IMPLICIT_DEF
110 DS_WRITE_B64_gfx9 %9, %10, 0, 0, implicit $exec 110 DS_WRITE_B64_gfx9 %9, %10, 0, 0, implicit $exec
111 DS_WRITE_B64_gfx9 %9, %11.sub1_sub2, 0, 0, implicit $exec 111 DS_WRITE_B64_gfx9 %9, %11.sub1_sub2, 0, 0, implicit $exec
112
113 ; Check aligned vgprs for FP32 Packed Math instructions.
114 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
115 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
116 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
117 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
118 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
119 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
120 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
121 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
122 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
123 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
124 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
125 ; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
126 %12:vreg_64 = IMPLICIT_DEF
127 %13:vreg_64_align2 = IMPLICIT_DEF
128 %14:areg_96_align2 = IMPLICIT_DEF
129 $vgpr3_vgpr4 = V_PK_MOV_B32 8, 0, 8, 0, 0, 0, 0, 0, 0, implicit $exec
130 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %12, 11, %13, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
131 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
132 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
133 $vgpr0_vgpr1 = V_PK_ADD_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
134 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %12, 11, %13, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
135 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %12, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
136 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
137 $vgpr0_vgpr1 = V_PK_MUL_F32 0, %14.sub1_sub2, 11, %13, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
138 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %12, 8, %13, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
139 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %12, 11, %14.sub0_sub1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
140 $vgpr0_vgpr1 = nofpexcept V_PK_FMA_F32 8, %13, 8, %13, 11, %14.sub1_sub2, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
112 ... 141 ...
113 142
114 # FIXME: Inline asm is not verified 143 # FIXME: Inline asm is not verified
115 # ; Check inline asm 144 # ; Check inline asm
116 # ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers *** 145 # ; XCHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***