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comparison llvm/test/TableGen/AsmPredicateCombining.td @ 236:c4bab56944e8 llvm-original

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LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 0572611fdcc8
children
comparison
equal deleted inserted replaced
232:70dce7da266c 236:c4bab56944e8
45 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">; 45 def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
46 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">; 46 def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
47 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">; 47 def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
48 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">; 48 def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
49 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">; 49 def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
50 def AsmCond4 : SubtargetFeature<"cond4", "cond4", "true", "">;
50 51
51 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>; 52 def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
52 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>; 53 def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
53 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>; 54 def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
55 def AsmPred4 : Predicate<"Pred4">, AssemblerPredicate<(all_of AsmCond4, (not (any_of AsmCond3a, AsmCond3b)))>;
54 // MATCHER: if (FB[arch::AsmCond1]) 56 // MATCHER: if (FB[arch::AsmCond1])
55 // MATCHER-NEXT: Features.set(Feature_AsmPred1Bit); 57 // MATCHER-NEXT: Features.set(Feature_AsmPred1Bit);
56 // MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b]) 58 // MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b])
57 // MATCHER-NEXT: Features.set(Feature_AsmPred2Bit); 59 // MATCHER-NEXT: Features.set(Feature_AsmPred2Bit);
58 // MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b])) 60 // MATCHER-NEXT: if (FB[arch::AsmCond3a] || FB[arch::AsmCond3b])
59 // MATCHER-NEXT: Features.set(Feature_AsmPred3Bit); 61 // MATCHER-NEXT: Features.set(Feature_AsmPred3Bit);
62 // MATCHER-NEXT: if (FB[arch::AsmCond4] && !(FB[arch::AsmCond3a] || FB[arch::AsmCond3b]))
63 // MATCHER-NEXT: Features.set(Feature_AsmPred4Bit);
60 64
61 def insn1 : TestInsn<1, [AsmPred1]>; 65 def insn1 : TestInsn<1, [AsmPred1]>;
62 // DISASS: return (Bits[arch::AsmCond1]); 66 // DISASS: return (Bits[arch::AsmCond1]);
63 67
64 def insn2 : TestInsn<2, [AsmPred2]>; 68 def insn2 : TestInsn<2, [AsmPred2]>;
65 // DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]) 69 // DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])
66 70
67 def insn3 : TestInsn<3, [AsmPred3]>; 71 def insn3 : TestInsn<3, [AsmPred3]>;
68 // DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])) 72 // DISASS: return (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])
69 73
70 def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>; 74 def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>;
71 // DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]) 75 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]))
72 76
73 def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>; 77 def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>;
74 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])) 78 // DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]))
75 79
76 def insn6 : TestInsn<6, []>; 80 def insn6 : TestInsn<6, []>;