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comparison test/CodeGen/AArch64/neon-mov.ll @ 33:e4204d083e25 LLVM3.5

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LLVM 3.5
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 14:32:10 +0900
parents 95c75e76d11b
children 54457678186b
comparison
equal deleted inserted replaced
1:f783a2dd24b1 33:e4204d083e25
1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 2
3 define <8 x i8> @movi8b() { 3 define <8 x i8> @movi8b() {
4 ;CHECK: movi {{v[0-31]+}}.8b, #0x8 4 ;CHECK: movi {{v[0-9]+}}.8b, #0x8
5 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 5 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
6 } 6 }
7 7
8 define <16 x i8> @movi16b() { 8 define <16 x i8> @movi16b() {
9 ;CHECK: movi {{v[0-31]+}}.16b, #0x8 9 ;CHECK: movi {{v[0-9]+}}.16b, #0x8
10 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 10 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
11 } 11 }
12 12
13 define <2 x i32> @movi2s_lsl0() { 13 define <2 x i32> @movi2s_lsl0() {
14 ;CHECK: movi {{v[0-31]+}}.2s, #0xff 14 ;CHECK: movi {{v[0-9]+}}.2s, #0xff
15 ret <2 x i32> < i32 255, i32 255 > 15 ret <2 x i32> < i32 255, i32 255 >
16 } 16 }
17 17
18 define <2 x i32> @movi2s_lsl8() { 18 define <2 x i32> @movi2s_lsl8() {
19 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #8 19 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #8
20 ret <2 x i32> < i32 65280, i32 65280 > 20 ret <2 x i32> < i32 65280, i32 65280 >
21 } 21 }
22 22
23 define <2 x i32> @movi2s_lsl16() { 23 define <2 x i32> @movi2s_lsl16() {
24 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #16 24 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #16
25 ret <2 x i32> < i32 16711680, i32 16711680 > 25 ret <2 x i32> < i32 16711680, i32 16711680 >
26 26
27 } 27 }
28 28
29 define <2 x i32> @movi2s_lsl24() { 29 define <2 x i32> @movi2s_lsl24() {
30 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #24 30 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #24
31 ret <2 x i32> < i32 4278190080, i32 4278190080 > 31 ret <2 x i32> < i32 4278190080, i32 4278190080 >
32 } 32 }
33 33
34 define <4 x i32> @movi4s_lsl0() { 34 define <4 x i32> @movi4s_lsl0() {
35 ;CHECK: movi {{v[0-31]+}}.4s, #0xff 35 ;CHECK: movi {{v[0-9]+}}.4s, #0xff
36 ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 > 36 ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
37 } 37 }
38 38
39 define <4 x i32> @movi4s_lsl8() { 39 define <4 x i32> @movi4s_lsl8() {
40 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #8 40 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #8
41 ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 > 41 ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
42 } 42 }
43 43
44 define <4 x i32> @movi4s_lsl16() { 44 define <4 x i32> @movi4s_lsl16() {
45 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #16 45 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #16
46 ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 > 46 ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
47 47
48 } 48 }
49 49
50 define <4 x i32> @movi4s_lsl24() { 50 define <4 x i32> @movi4s_lsl24() {
51 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #24 51 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #24
52 ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 > 52 ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
53 } 53 }
54 54
55 define <4 x i16> @movi4h_lsl0() { 55 define <4 x i16> @movi4h_lsl0() {
56 ;CHECK: movi {{v[0-31]+}}.4h, #0xff 56 ;CHECK: movi {{v[0-9]+}}.4h, #0xff
57 ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 > 57 ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
58 } 58 }
59 59
60 define <4 x i16> @movi4h_lsl8() { 60 define <4 x i16> @movi4h_lsl8() {
61 ;CHECK: movi {{v[0-31]+}}.4h, #0xff, lsl #8 61 ;CHECK: movi {{v[0-9]+}}.4h, #0xff, lsl #8
62 ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 > 62 ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
63 } 63 }
64 64
65 define <8 x i16> @movi8h_lsl0() { 65 define <8 x i16> @movi8h_lsl0() {
66 ;CHECK: movi {{v[0-31]+}}.8h, #0xff 66 ;CHECK: movi {{v[0-9]+}}.8h, #0xff
67 ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 > 67 ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
68 } 68 }
69 69
70 define <8 x i16> @movi8h_lsl8() { 70 define <8 x i16> @movi8h_lsl8() {
71 ;CHECK: movi {{v[0-31]+}}.8h, #0xff, lsl #8 71 ;CHECK: movi {{v[0-9]+}}.8h, #0xff, lsl #8
72 ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 72 ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
73 } 73 }
74 74
75 75
76 define <2 x i32> @mvni2s_lsl0() { 76 define <2 x i32> @mvni2s_lsl0() {
77 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10 77 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10
78 ret <2 x i32> < i32 4294967279, i32 4294967279 > 78 ret <2 x i32> < i32 4294967279, i32 4294967279 >
79 } 79 }
80 80
81 define <2 x i32> @mvni2s_lsl8() { 81 define <2 x i32> @mvni2s_lsl8() {
82 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #8 82 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #8
83 ret <2 x i32> < i32 4294963199, i32 4294963199 > 83 ret <2 x i32> < i32 4294963199, i32 4294963199 >
84 } 84 }
85 85
86 define <2 x i32> @mvni2s_lsl16() { 86 define <2 x i32> @mvni2s_lsl16() {
87 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #16 87 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #16
88 ret <2 x i32> < i32 4293918719, i32 4293918719 > 88 ret <2 x i32> < i32 4293918719, i32 4293918719 >
89 } 89 }
90 90
91 define <2 x i32> @mvni2s_lsl24() { 91 define <2 x i32> @mvni2s_lsl24() {
92 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #24 92 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #24
93 ret <2 x i32> < i32 4026531839, i32 4026531839 > 93 ret <2 x i32> < i32 4026531839, i32 4026531839 >
94 } 94 }
95 95
96 define <4 x i32> @mvni4s_lsl0() { 96 define <4 x i32> @mvni4s_lsl0() {
97 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10 97 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10
98 ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 > 98 ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
99 } 99 }
100 100
101 define <4 x i32> @mvni4s_lsl8() { 101 define <4 x i32> @mvni4s_lsl8() {
102 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #8 102 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #8
103 ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 > 103 ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
104 } 104 }
105 105
106 define <4 x i32> @mvni4s_lsl16() { 106 define <4 x i32> @mvni4s_lsl16() {
107 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #16 107 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #16
108 ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 > 108 ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
109 109
110 } 110 }
111 111
112 define <4 x i32> @mvni4s_lsl24() { 112 define <4 x i32> @mvni4s_lsl24() {
113 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #24 113 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #24
114 ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 > 114 ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
115 } 115 }
116 116
117 117
118 define <4 x i16> @mvni4h_lsl0() { 118 define <4 x i16> @mvni4h_lsl0() {
119 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10 119 ;CHECK: mvni {{v[0-9]+}}.4h, #0x10
120 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > 120 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
121 } 121 }
122 122
123 define <4 x i16> @mvni4h_lsl8() { 123 define <4 x i16> @mvni4h_lsl8() {
124 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10, lsl #8 124 ;CHECK: mvni {{v[0-9]+}}.4h, #0x10, lsl #8
125 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > 125 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
126 } 126 }
127 127
128 define <8 x i16> @mvni8h_lsl0() { 128 define <8 x i16> @mvni8h_lsl0() {
129 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10 129 ;CHECK: mvni {{v[0-9]+}}.8h, #0x10
130 ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 > 130 ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
131 } 131 }
132 132
133 define <8 x i16> @mvni8h_lsl8() { 133 define <8 x i16> @mvni8h_lsl8() {
134 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10, lsl #8 134 ;CHECK: mvni {{v[0-9]+}}.8h, #0x10, lsl #8
135 ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 > 135 ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
136 } 136 }
137 137
138 138
139 define <2 x i32> @movi2s_msl8(<2 x i32> %a) { 139 define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
140 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #8 140 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #8
141 ret <2 x i32> < i32 65535, i32 65535 > 141 ret <2 x i32> < i32 65535, i32 65535 >
142 } 142 }
143 143
144 define <2 x i32> @movi2s_msl16() { 144 define <2 x i32> @movi2s_msl16() {
145 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #16 145 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #16
146 ret <2 x i32> < i32 16777215, i32 16777215 > 146 ret <2 x i32> < i32 16777215, i32 16777215 >
147 } 147 }
148 148
149 149
150 define <4 x i32> @movi4s_msl8() { 150 define <4 x i32> @movi4s_msl8() {
151 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #8 151 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #8
152 ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 > 152 ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
153 } 153 }
154 154
155 define <4 x i32> @movi4s_msl16() { 155 define <4 x i32> @movi4s_msl16() {
156 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #16 156 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #16
157 ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 > 157 ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
158 } 158 }
159 159
160 define <2 x i32> @mvni2s_msl8() { 160 define <2 x i32> @mvni2s_msl8() {
161 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #8 161 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #8
162 ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264> 162 ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
163 } 163 }
164 164
165 define <2 x i32> @mvni2s_msl16() { 165 define <2 x i32> @mvni2s_msl16() {
166 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #16 166 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #16
167 ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504> 167 ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
168 } 168 }
169 169
170 define <4 x i32> @mvni4s_msl8() { 170 define <4 x i32> @mvni4s_msl8() {
171 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #8 171 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #8
172 ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264> 172 ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
173 } 173 }
174 174
175 define <4 x i32> @mvni4s_msl16() { 175 define <4 x i32> @mvni4s_msl16() {
176 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #16 176 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #16
177 ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504> 177 ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
178 } 178 }
179 179
180 define <2 x i64> @movi2d() { 180 define <2 x i64> @movi2d() {
181 ;CHECK: movi {{v[0-31]+}}.2d, #0xff0000ff0000ffff 181 ;CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
182 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > 182 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
183 } 183 }
184 184
185 define <1 x i64> @movid() { 185 define <1 x i64> @movid() {
186 ;CHECK: movi {{d[0-31]+}}, #0xff0000ff0000ffff 186 ;CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
187 ret <1 x i64> < i64 18374687574888349695 > 187 ret <1 x i64> < i64 18374687574888349695 >
188 } 188 }
189 189
190 define <2 x float> @fmov2s() { 190 define <2 x float> @fmov2s() {
191 ;CHECK: fmov {{v[0-31]+}}.2s, #-12.00000000 191 ;CHECK: fmov {{v[0-9]+}}.2s, #-12.00000000
192 ret <2 x float> < float -1.2e1, float -1.2e1> 192 ret <2 x float> < float -1.2e1, float -1.2e1>
193 } 193 }
194 194
195 define <4 x float> @fmov4s() { 195 define <4 x float> @fmov4s() {
196 ;CHECK: fmov {{v[0-31]+}}.4s, #-12.00000000 196 ;CHECK: fmov {{v[0-9]+}}.4s, #-12.00000000
197 ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1> 197 ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
198 } 198 }
199 199
200 define <2 x double> @fmov2d() { 200 define <2 x double> @fmov2d() {
201 ;CHECK: fmov {{v[0-31]+}}.2d, #-12.00000000 201 ;CHECK: fmov {{v[0-9]+}}.2d, #-12.00000000
202 ret <2 x double> < double -1.2e1, double -1.2e1> 202 ret <2 x double> < double -1.2e1, double -1.2e1>
203 } 203 }
204 204
205 205 define <2 x i32> @movi1d_1() {
206 ; CHECK: movi d0, #0xffffffff0000
207 ret <2 x i32> < i32 -65536, i32 65535>
208 }
209
210
211 declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
212 define <2 x i32> @movi1d() {
213 ; CHECK: movi d1, #0xffffffff0000
214 %1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
215 ret <2 x i32> %1
216 }
217