diff lld/test/ELF/riscv-ifunc-nonpreemptible.s @ 173:0572611fdcc8 llvm10 llvm12

reorgnization done
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 11:55:54 +0900
parents 1d019706d866
children 2e18cbf3894f
line wrap: on
line diff
--- a/lld/test/ELF/riscv-ifunc-nonpreemptible.s	Mon May 25 11:50:15 2020 +0900
+++ b/lld/test/ELF/riscv-ifunc-nonpreemptible.s	Mon May 25 11:55:54 2020 +0900
@@ -17,11 +17,11 @@
 
 # SYM32: 0001190 0 FUNC GLOBAL DEFAULT {{.*}} func
 
-# DIS32:      _start:
+# DIS32:      <_start>:
 # DIS32-NEXT: 1180: auipc a0, 0
 # DIS32-NEXT:       addi a0, a0, 16
 # DIS32:      Disassembly of section .iplt:
-# DIS32:      func:
+# DIS32:      <func>:
 ## 32-bit: &.got.plt[func]-. = 0x3218-0x1190 = 4096*2+136
 # DIS32-NEXT: 1190: auipc t3, 2
 # DIS32-NEXT:       lw t3, 136(t3)
@@ -34,11 +34,11 @@
 
 # SYM64: 000000000001270 0 FUNC GLOBAL DEFAULT {{.*}} func
 
-# DIS64:      _start:
+# DIS64:      <_start>:
 # DIS64-NEXT: 1264: auipc a0, 0
 # DIS64-NEXT:       addi a0, a0, 12
 # DIS64:      Disassembly of section .iplt:
-# DIS64:      func:
+# DIS64:      <func>:
 ## 64-bit: &.got.plt[func]-. = 0x3370-0x1270 = 4096*2+256
 # DIS64-NEXT: 1270: auipc t3, 2
 # DIS64-NEXT:       ld t3, 256(t3)