Mercurial > hg > CbC > CbC_llvm
diff lib/Target/Mips/Mips.td @ 120:1172e4bd9c6f
update 4.0.0
author | mir3636 |
---|---|
date | Fri, 25 Nov 2016 19:14:25 +0900 |
parents | 7d135dc70f03 |
children | 803732b1fca8 |
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--- a/lib/Target/Mips/Mips.td Tue Jan 26 22:56:36 2016 +0900 +++ b/lib/Target/Mips/Mips.td Fri Nov 25 19:14:25 2016 +0900 @@ -24,6 +24,8 @@ list<Predicate> EncodingPredicates = []; // Predicates for the GPR size such as IsGP64bit list<Predicate> GPRPredicates = []; + // Predicates for the PTR size such as IsPTR64bit + list<Predicate> PTRPredicates = []; // Predicates for the FGR size and layout such as IsFP64bit list<Predicate> FGRPredicates = []; // Predicates for the instruction group membership such as ISA's and ASE's @@ -34,6 +36,7 @@ list<Predicate> AdditionalPredicates = []; list<Predicate> Predicates = !listconcat(EncodingPredicates, GPRPredicates, + PTRPredicates, FGRPredicates, InsnPredicates, HardFloatPredicate, @@ -54,6 +57,10 @@ include "MipsInstrInfo.td" include "MipsCallingConv.td" +// Avoid forward declaration issues. +include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" + def MipsInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// @@ -62,6 +69,8 @@ def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", "Disable SVR4-style position-independent code">; +def FeaturePTR64Bit : SubtargetFeature<"ptr64", "IsPTR64bit", "true", + "Pointers are 64-bit wide">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", @@ -183,7 +192,7 @@ "The P5600 Processor", [FeatureMips32r5]>; class Proc<string Name, list<SubtargetFeature> Features> - : Processor<Name, MipsGenericItineraries, Features>; + : ProcessorModel<Name, MipsGenericModel, Features>; def : Proc<"mips1", [FeatureMips1]>; def : Proc<"mips2", [FeatureMips2]>;