--- a/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir	Wed Nov 09 17:47:54 2022 +0900
+++ b/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir	Fri Aug 18 09:04:13 2023 +0900
@@ -1,4 +1,4 @@
-# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s
 
 # Test that register coalescing does not allow a call to
 # LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have
@@ -8,7 +8,7 @@
 # CHECK: DBG_VALUE{{.*}} %13.sub2
 
 --- |
-  define amdgpu_kernel void @test(i32 addrspace(1)* %out) { ret void }
+  define amdgpu_kernel void @test(ptr addrspace(1) %out) { ret void }
 
   !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
   !1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
@@ -56,8 +56,8 @@
 
     %3 = COPY killed $vgpr0
     %0 = COPY killed $sgpr0_sgpr1
-    %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`)
-    %5 = S_LOAD_DWORD_IMM killed %0, 13, 0 :: (non-temporal dereferenceable invariant load (s32) from `i32 addrspace(4)* undef`)
+    %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) undef`)
+    %5 = S_LOAD_DWORD_IMM killed %0, 13, 0 :: (non-temporal dereferenceable invariant load (s32) from `ptr addrspace(4) undef`)
     %18 = V_ASHRREV_I32_e32 31, %3, implicit $exec
     undef %19.sub0 = COPY killed %3
     %19.sub1 = COPY killed %18
@@ -70,7 +70,7 @@
     %13.sub2_sub3 = COPY killed %12
     %20 = V_LSHL_B64_e64 killed %19, 2, implicit $exec
     %16 = COPY killed %5
-    BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out)
+    BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out)
     S_ENDPGM 0
 
 ...