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diff llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents 1d019706d866
children
line wrap: on
line diff
--- a/llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll	Wed Nov 09 17:47:54 2022 +0900
+++ b/llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll	Fri Aug 18 09:04:13 2023 +0900
@@ -6,9 +6,9 @@
 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00
 
-define amdgpu_kernel void @vtx_fetch32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
-  %v = load i32, i32 addrspace(1)* %in
-  store i32 %v, i32 addrspace(1)* %out
+define amdgpu_kernel void @vtx_fetch32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+  %v = load i32, ptr addrspace(1) %in
+  store i32 %v, ptr addrspace(1) %out
   ret void
 }
 
@@ -16,9 +16,9 @@
 ; EG: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00
 ; CM: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[SRC]],0x00,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x00,0x00
 
-define amdgpu_kernel void @vtx_fetch128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
-  %v = load <4 x i32>, <4 x i32> addrspace(1)* %in
-  store <4 x i32> %v, <4 x i32> addrspace(1)* %out
+define amdgpu_kernel void @vtx_fetch128(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+  %v = load <4 x i32>, ptr addrspace(1) %in
+  store <4 x i32> %v, ptr addrspace(1) %out
   ret void
 }
 
@@ -26,9 +26,9 @@
 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00
 
-define amdgpu_kernel void @vtx_fetch32_id3(i32 addrspace(1)* %out, i32 addrspace(7)* %in) {
-  %v = load i32, i32 addrspace(7)* %in
-  store i32 %v, i32 addrspace(1)* %out
+define amdgpu_kernel void @vtx_fetch32_id3(ptr addrspace(1) %out, ptr addrspace(7) %in) {
+  %v = load i32, ptr addrspace(7) %in
+  store i32 %v, ptr addrspace(1) %out
   ret void
 }
 
@@ -38,9 +38,9 @@
 
 @t = internal addrspace(4) constant [4 x i32] [i32 0, i32 1, i32 2, i32 3]
 
-define amdgpu_kernel void @vtx_fetch32_id2(i32 addrspace(1)* %out, i32 %in) {
-  %a = getelementptr inbounds [4 x i32], [4 x i32] addrspace(4)* @t, i32 0, i32 %in
-  %v = load i32, i32 addrspace(4)* %a
-  store i32 %v, i32 addrspace(1)* %out
+define amdgpu_kernel void @vtx_fetch32_id2(ptr addrspace(1) %out, i32 %in) {
+  %a = getelementptr inbounds [4 x i32], ptr addrspace(4) @t, i32 0, i32 %in
+  %v = load i32, ptr addrspace(4) %a
+  store i32 %v, ptr addrspace(1) %out
   ret void
 }