--- a/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll	Wed Nov 09 17:47:54 2022 +0900
+++ b/llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll	Fri Aug 18 09:04:13 2023 +0900
@@ -4,7 +4,7 @@
 ;CHECK: {{^}}fill3d:
 ;CHECK-NOT: MULLO_INT T[0-9]+
 
-define amdgpu_kernel void @fill3d(i32 addrspace(1)* nocapture %out) #0 {
+define amdgpu_kernel void @fill3d(ptr addrspace(1) nocapture %out) #0 {
 entry:
   %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
   %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
@@ -30,8 +30,8 @@
   %z.i8.i = tail call i32 @llvm.r600.read.tidig.z() #1
   %add.i = add i32 %z.i8.i, %mul33.i
   %add13 = add i32 %add.i, %add
-  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add13
-  store i32 %mul3, i32 addrspace(1)* %arrayidx, align 4
+  %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %add13
+  store i32 %mul3, ptr addrspace(1) %arrayidx, align 4
   ret void
 }
 
@@ -78,4 +78,4 @@
 
 !0 = !{null}
 !1 = !{null}
-!2 = !{void (i32 addrspace(1)*)* @fill3d}
+!2 = !{ptr @fill3d}