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diff llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children
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--- a/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst	Mon May 25 11:55:54 2020 +0900
+++ b/llvm/docs/AMDGPU/gfx9_offset_smem_plain.rst	Tue Jun 08 06:07:14 2021 +0900
@@ -15,8 +15,6 @@
 * If offset is specified as a register, it supplies an unsigned byte offset.
 * If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
 
-.. WARNING:: Assembler currently supports 20-bit unsigned offsets only. Use :ref:`uimm20<amdgpu_synid_uimm20>` instead of :ref:`simm21<amdgpu_synid_simm21>`.
-
 *Size:* 1 dword.
 
 *Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`