diff llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td @ 207:2e18cbf3894f

LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children
line wrap: on
line diff
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td	Mon May 25 11:55:54 2020 +0900
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/InitValue.td	Tue Jun 08 06:07:14 2021 +0900
@@ -16,7 +16,7 @@
     field bits<16> SoftFail = 0;
     bits<8> factor;
     let factor{0} = 0; // zero initial value
-    let Inst{15-8} = factor{7-0};
+    let Inst{15...8} = factor{7...0};
     }
 
 def bar : Instruction {
@@ -25,7 +25,7 @@
     field bits<16> SoftFail = 0;
     bits<8> factor;
     let factor{0} = 1; // non-zero initial value
-    let Inst{15-8} = factor{7-0};
+    let Inst{15...8} = factor{7...0};
     }
 
 def bax : Instruction {
@@ -34,13 +34,13 @@
     field bits<16> SoftFail = 0;
     bits<33> factor;
     let factor{32} = 1; // non-zero initial value
-    let Inst{15-8} = factor{32-25};
+    let Inst{15...8} = factor{32...25};
     }
 
 }
 
 // CHECK: tmp = fieldFromInstruction(insn, 9, 7) << 1;
 // CHECK: tmp = 0x1;
-// CHECK: tmp |= fieldFromInstruction(insn, 9, 7) << 1;
+// CHECK: insertBits(tmp, fieldFromInstruction(insn, 9, 7), 1, 7);
 // CHECK: tmp = 0x100000000;
-// CHECK: tmp |= fieldFromInstruction(insn, 8, 7) << 25;
+// CHECK: insertBits(tmp, fieldFromInstruction(insn, 8, 7), 25, 7);