--- a/test/CodeGen/AArch64/arm64-umaxv.ll	Fri Feb 16 19:10:49 2018 +0900
+++ b/test/CodeGen/AArch64/arm64-umaxv.ll	Sat Feb 17 09:57:20 2018 +0900
@@ -89,7 +89,7 @@
 define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
@@ -101,7 +101,7 @@
 define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
 ; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
@@ -113,7 +113,7 @@
 define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
 ; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
@@ -124,7 +124,7 @@
 define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
 ; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
@@ -136,7 +136,7 @@
 define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
 ; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
@@ -148,7 +148,7 @@
 define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
 ; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
 ; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]
 ; CHECK-NEXT: ret
 entry:
   %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)