Mercurial > hg > CbC > CbC_llvm
diff lib/Target/ARM/ARM.td @ 148:63bd29f05246
merged
| author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Wed, 14 Aug 2019 19:46:37 +0900 |
| parents | c2174574ed3a |
| children |
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--- a/lib/Target/ARM/ARM.td Sun Dec 23 19:23:36 2018 +0900 +++ b/lib/Target/ARM/ARM.td Wed Aug 14 19:46:37 2019 +0900 @@ -1,9 +1,8 @@ //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -33,12 +32,59 @@ // // Floating Point, HW Division and Neon Support -def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", - "Enable VFP2 instructions">; + +// FP loads/stores/moves, shared between VFP and MVE (even in the integer-only +// version). +def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", + "Enable FP registers">; + +// 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 +// extension) and MVE (even in the integer-only version). +def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", + "Enable 16-bit FP registers", + [FeatureFPRegs]>; + +def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", + "Enable 64-bit FP registers", + [FeatureFPRegs]>; + +def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", + "Floating point unit supports " + "double precision", + [FeatureFPRegs64]>; + +def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", + "Extend FP to 32 double registers">; -def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", - "Enable VFP3 instructions", - [FeatureVFP2]>; +multiclass VFPver<string name, string query, string description, + list<SubtargetFeature> prev = [], + list<SubtargetFeature> otherimplies = []> { + def _D16_SP: SubtargetFeature< + name#"d16sp", query#"D16SP", "true", + description#" with only 16 d-registers and no double precision", + !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) # otherimplies>; + def _SP: SubtargetFeature< + name#"sp", query#"SP", "true", + description#" with no double precision", + !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) # + otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; + def _D16: SubtargetFeature< + name#"d16", query#"D16", "true", + description#" with only 16 d-registers", + !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) # + otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>; + def "": SubtargetFeature< + name, query, "true", description, + prev # otherimplies # [ + !cast<SubtargetFeature>(NAME # "_D16"), + !cast<SubtargetFeature>(NAME # "_SP")]>; +} + +defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions", + [], [FeatureFPRegs]>; + +defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", + [FeatureVFP2]>; def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable NEON instructions", @@ -48,25 +94,21 @@ "Enable half-precision " "floating point">; -def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", - "Enable VFP4 instructions", - [FeatureVFP3, FeatureFP16]>; +defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", + [FeatureVFP3], [FeatureFP16]>; -def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", - "true", "Enable ARMv8 FP", - [FeatureVFP4]>; +defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", + [FeatureVFP4]>; def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", "Enable full half-precision " "floating point", - [FeatureFPARMv8]>; + [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; -def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", - "Floating point unit supports " - "single precision only">; - -def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", - "Restrict FP to 16 double registers">; +def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", + "Enable full half-precision " + "floating point fml instructions", + [FeatureFullFP16]>; def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb", "true", @@ -109,10 +151,16 @@ "Enable support for ARMv8-M " "Security Extensions">; +def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", + "Enable SHA1 and SHA256 support", [FeatureNEON]>; + +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES support", [FeatureNEON]>; + def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable support for " "Cryptography extensions", - [FeatureNEON]>; + [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable support for CRC instructions">; @@ -135,6 +183,10 @@ def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", "CPU fuses AES crypto operations">; +// Fast execution of bottom and top halves of literal generation +def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", + "CPU fuses literal generation operations">; + // The way of reading thread pointer def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", "Reading thread pointer from register">; @@ -184,11 +236,22 @@ "SlowLoadDSubregister", "true", "Loading into D subregs is slow">; +def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", + "UseWideStrideVFP", "true", + "Use a wide stride when allocating VFP registers">; + // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", "DontWidenVMOVS", "true", "Don't widen VMOVS to VMOVD">; +// Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different +// VFP register widths. +def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", + "SplatVFPToNeon", "true", + "Splat register from VFP to NEON", + [FeatureDontWidenVMOVS]>; + // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", @@ -239,6 +302,18 @@ def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; +def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", + "Prefer 32-bit alignment for loops">; + +def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1", + "Model MVE instructions as a 1 beat per tick architecture">; + +def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2", + "Model MVE instructions as a 2 beats per tick architecture">; + +def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4", + "Model MVE instructions as a 4 beats per tick architecture">; + /// Some instructions update CPSR partially, which can add false dependency for /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is /// mapped to a separate physical register. Avoid partial CPSR update for these @@ -330,6 +405,21 @@ "DisablePostRAScheduler", "true", "Don't schedule again after register allocation">; +// Enable use of alias analysis during code generation +def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", + "Use alias analysis during codegen">; + +// Armv8.5-A extensions + +def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", + "Enable v8.5a Speculation Barrier" >; + +// Armv8.1-M extensions + +def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", + "Enable Low Overhead Branch " + "extensions">; + //===----------------------------------------------------------------------===// // ARM architecture class // @@ -415,6 +505,27 @@ "Support ARM v8.3a instructions", [HasV8_2aOps]>; +def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", + "Support ARM v8.4a instructions", + [HasV8_3aOps, FeatureDotProd]>; + +def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", + "Support ARM v8.5a instructions", + [HasV8_4aOps, FeatureSB]>; + +def HasV8_1MMainlineOps : SubtargetFeature< + "v8.1m.main", "HasV8_1MMainlineOps", "true", + "Support ARM v8-1M Mainline instructions", + [HasV8MMainlineOps]>; +def HasMVEIntegerOps : SubtargetFeature< + "mve", "HasMVEIntegerOps", "true", + "Support M-Class Vector Extension with integer ops", + [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; +def HasMVEFloatOps : SubtargetFeature< + "mve.fp", "HasMVEFloatOps", "true", + "Support M-Class Vector Extension with integer and floating ops", + [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; + //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -449,6 +560,8 @@ "Cortex-A73 ARM processors", []>; def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", "Cortex-A75 ARM processors", []>; +def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", + "Cortex-A76 ARM processors", []>; def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; @@ -457,8 +570,25 @@ def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", "Swift ARM processors", []>; -def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", - "Samsung Exynos-Mx processors", []>; +def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", + "Samsung Exynos processors", + [FeatureZCZeroing, + FeatureUseWideStrideVFP, + FeatureUseAA, + FeatureSplatVFPToNeon, + FeatureSlowVGETLNi32, + FeatureSlowVDUP32, + FeatureSlowFPBrcc, + FeatureProfUnpredicate, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureHasSlowFPVMLx, + FeatureHasRetAddrStack, + FeatureFuseLiterals, + FeatureFuseAES, + FeatureExpandMLx, + FeatureCrypto, + FeatureCRC]>; def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", "Cortex-R4 ARM processors", []>; @@ -522,13 +652,15 @@ FeatureNoARM, ModeThumb, FeatureDB, - FeatureMClass]>; + FeatureMClass, + FeatureStrictAlign]>; def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, - FeatureMClass]>; + FeatureMClass, + FeatureStrictAlign]>; def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, FeatureNEON, @@ -618,6 +750,34 @@ FeatureCRC, FeatureRAS]>; +def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + +def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, @@ -638,7 +798,8 @@ FeatureV7Clrex, Feature8MSecExt, FeatureAcquireRelease, - FeatureMClass]>; + FeatureMClass, + FeatureStrictAlign]>; def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", [HasV8MMainlineOps, @@ -650,6 +811,18 @@ FeatureAcquireRelease, FeatureMClass]>; +def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", + [HasV8_1MMainlineOps, + FeatureNoARM, + ModeThumb, + FeatureDB, + FeatureHWDivThumb, + Feature8MSecExt, + FeatureAcquireRelease, + FeatureMClass, + FeatureRAS, + FeatureLOB]>; + // Aliases def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; @@ -663,6 +836,7 @@ // ARM schedules. //===----------------------------------------------------------------------===// // +include "ARMPredicates.td" include "ARMSchedule.td" //===----------------------------------------------------------------------===// @@ -788,6 +962,7 @@ def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, FeatureDontWidenVMOVS, + FeatureSplatVFPToNeon, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureTrustZone, @@ -822,6 +997,7 @@ FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, + FeatureUseWideStrideVFP, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, @@ -846,14 +1022,12 @@ FeatureHasRetAddrStack, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, - FeatureVFP3, - FeatureD16, + FeatureVFP3_D16, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, FeatureHasRetAddrStack, - FeatureVFP3, - FeatureD16, + FeatureVFP3_D16, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, @@ -861,8 +1035,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, FeatureHasRetAddrStack, - FeatureVFP3, - FeatureD16, + FeatureVFP3_D16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, @@ -872,8 +1045,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, FeatureHasRetAddrStack, - FeatureVFP3, - FeatureD16, + FeatureVFP3_D16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, @@ -881,34 +1053,52 @@ FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; -def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, +def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, ProcM3, + FeaturePrefLoopAlign32, + FeatureUseMISched, + FeatureUseAA, FeatureHasNoBranchPredictor]>; -def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, +def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, ProcM3, + FeatureUseMISched, + FeatureUseAA, FeatureHasNoBranchPredictor]>; -def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, - FeatureVFP4, - FeatureVFPOnlySP, - FeatureD16, +def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, + FeatureVFP4_D16_SP, + FeaturePrefLoopAlign32, + FeatureHasSlowFPVMLx, + FeatureUseMISched, + FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-m7", [ARMv7em, - FeatureFPARMv8, - FeatureD16]>; + FeatureFPARMv8_D16]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; -def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, +def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, FeatureDSP, - FeatureFPARMv8, - FeatureD16, - FeatureVFPOnlySP, + FeatureFPARMv8_D16_SP, + FeaturePrefLoopAlign32, + FeatureHasSlowFPVMLx, + FeatureUseMISched, + FeatureUseAA, FeatureHasNoBranchPredictor]>; +def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, + FeatureDSP, + FeatureFPARMv8_D16_SP, + FeaturePrefLoopAlign32, + FeatureHasSlowFPVMLx, + FeatureUseMISched, + FeatureUseAA, + FeatureHasNoBranchPredictor]>; + + def : ProcNoItin<"cortex-a32", [ARMv8a, FeatureHWDivThumb, FeatureHWDivARM, @@ -942,7 +1132,7 @@ FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR]>; -def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, +def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, @@ -959,6 +1149,29 @@ FeatureHWDivARM, FeatureDotProd]>; +def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFullFP16, + FeatureDotProd]>; + +def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureFullFP16, + FeatureDotProd]>; + +def : ProcNoItin<"neoverse-n1", [ARMv82a, + FeatureHWDivThumb, + FeatureHWDivARM, + FeatureCrypto, + FeatureCRC, + FeatureDotProd]>; + def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, @@ -974,23 +1187,15 @@ FeatureZCZeroing, FeatureNoPostRASched]>; -def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, - FeatureHWDivThumb, - FeatureHWDivARM, - FeatureCrypto, - FeatureCRC]>; - -def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, - FeatureHWDivThumb, - FeatureHWDivARM, - FeatureCrypto, - FeatureCRC]>; - -def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, - FeatureHWDivThumb, - FeatureHWDivARM, - FeatureCrypto, - FeatureCRC]>; +def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; +def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; +def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; +def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, + FeatureFullFP16, + FeatureDotProd]>; +def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, + FeatureFullFP16, + FeatureDotProd]>; def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, FeatureHWDivThumb, @@ -999,7 +1204,9 @@ FeatureCRC]>; def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, - FeatureFPAO]>; + FeatureUseMISched, + FeatureFPAO, + FeatureUseAA]>; //===----------------------------------------------------------------------===// // Register File Description @@ -1043,4 +1250,5 @@ let AssemblyWriters = [ARMAsmWriter]; let AssemblyParsers = [ARMAsmParser]; let AssemblyParserVariants = [ARMAsmParserVariant]; + let AllowRegisterRenaming = 1; }