Mercurial > hg > CbC > CbC_llvm
diff test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir @ 121:803732b1fca8
LLVM 5.0
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 17:07:41 +0900 |
| parents | |
| children | 3a76565eade5 |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir Fri Oct 27 17:07:41 2017 +0900 @@ -0,0 +1,40 @@ +# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s +... +# GCN-LABEL: name: fold_imm_non_ssa{{$}} +# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit %exec +# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def %vcc, implicit %exec + +name: fold_imm_non_ssa +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sreg_64 } +body: | + bb.0: + %0 = COPY undef %0 + %0 = V_MOV_B32_e32 123, implicit %exec + %1 = V_MOV_B32_e32 456, implicit %exec + %2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec + S_ENDPGM + +... +# GCN-LABEL: name: fold_partially_defined_superreg{{$}} +# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit %exec +# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def %vcc, implicit %exec +name: fold_partially_defined_superreg +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: vreg_64 } +body: | + bb.0: + undef %3.sub0 = V_MOV_B32_e32 123, implicit %exec, implicit-def %3 + %1 = V_MOV_B32_e32 456, implicit %exec + %2, %vcc = V_ADD_I32_e64 %3.sub0, %1, implicit %exec + S_ENDPGM + +...