Mercurial > hg > CbC > CbC_llvm
diff lib/Target/Mips/MipsSchedule.td @ 95:afa8332a0e37 LLVM3.8
LLVM 3.8
| author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 13 Oct 2015 17:48:58 +0900 |
| parents | 54457678186b |
| children | 1172e4bd9c6f |
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--- a/lib/Target/Mips/MipsSchedule.td Wed Feb 18 14:56:07 2015 +0900 +++ b/lib/Target/Mips/MipsSchedule.td Tue Oct 13 17:48:58 2015 +0900 @@ -16,8 +16,8 @@ //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for Mips //===----------------------------------------------------------------------===// -def IIAlu : InstrItinClass; -def IIBranch : InstrItinClass; +// IIM16Alu is a placeholder class for most MIPS16 instructions. +def IIM16Alu : InstrItinClass; def IIPseudo : InstrItinClass; def II_ABS : InstrItinClass; @@ -28,7 +28,19 @@ def II_ADD_S : InstrItinClass; def II_AND : InstrItinClass; def II_ANDI : InstrItinClass; +def II_B : InstrItinClass; def II_BADDU : InstrItinClass; +def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32 +def II_BC : InstrItinClass; +def II_BC1F : InstrItinClass; +def II_BC1FL : InstrItinClass; +def II_BC1T : InstrItinClass; +def II_BC1TL : InstrItinClass; +def II_BCC : InstrItinClass; // beq and bne +def II_BCCZ : InstrItinClass; // b[gl][et]z +def II_BCCZAL : InstrItinClass; // bgezal and bltzal +def II_BCCZALS : InstrItinClass; // bgezals and bltzals +def II_BCCZC : InstrItinClass; // beqzc, bnezc def II_CEIL : InstrItinClass; def II_CFC1 : InstrItinClass; def II_CLO : InstrItinClass; @@ -65,22 +77,42 @@ def II_DSRLV : InstrItinClass; def II_DSUBU : InstrItinClass; def II_DSUB : InstrItinClass; +def II_EXT : InstrItinClass; // Any EXT instruction def II_FLOOR : InstrItinClass; +def II_INS : InstrItinClass; // Any INS instruction +def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo. +def II_J : InstrItinClass; +def II_JAL : InstrItinClass; +def II_JALR : InstrItinClass; +def II_JALRC : InstrItinClass; +def II_JALRS : InstrItinClass; +def II_JALS : InstrItinClass; +def II_JR : InstrItinClass; +def II_JRADDIUSP : InstrItinClass; +def II_JRC : InstrItinClass; +def II_ReturnPseudo : InstrItinClass; // Return pseudo. def II_LB : InstrItinClass; +def II_LBE : InstrItinClass; def II_LBU : InstrItinClass; +def II_LBUE : InstrItinClass; def II_LD : InstrItinClass; def II_LDC1 : InstrItinClass; def II_LDL : InstrItinClass; def II_LDR : InstrItinClass; def II_LDXC1 : InstrItinClass; def II_LH : InstrItinClass; +def II_LHE : InstrItinClass; def II_LHU : InstrItinClass; +def II_LHUE : InstrItinClass; def II_LUI : InstrItinClass; def II_LUXC1 : InstrItinClass; def II_LW : InstrItinClass; +def II_LWE : InstrItinClass; def II_LWC1 : InstrItinClass; def II_LWL : InstrItinClass; +def II_LWLE : InstrItinClass; def II_LWR : InstrItinClass; +def II_LWRE : InstrItinClass; def II_LWU : InstrItinClass; def II_LWXC1 : InstrItinClass; def II_MADD : InstrItinClass; @@ -132,6 +164,7 @@ def II_ROUND : InstrItinClass; def II_SAVE : InstrItinClass; def II_SB : InstrItinClass; +def II_SBE : InstrItinClass; def II_SD : InstrItinClass; def II_SDC1 : InstrItinClass; def II_SDL : InstrItinClass; @@ -142,6 +175,7 @@ def II_SEQ_SNE : InstrItinClass; // seq and sne def II_SEQI_SNEI : InstrItinClass; // seqi and snei def II_SH : InstrItinClass; +def II_SHE : InstrItinClass; def II_SLL : InstrItinClass; def II_SLLV : InstrItinClass; def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu @@ -157,11 +191,15 @@ def II_SUB_S : InstrItinClass; def II_SUXC1 : InstrItinClass; def II_SW : InstrItinClass; +def II_SWE : InstrItinClass; def II_SWC1 : InstrItinClass; def II_SWL : InstrItinClass; +def II_SWLE : InstrItinClass; def II_SWR : InstrItinClass; +def II_SWRE : InstrItinClass; def II_SWXC1 : InstrItinClass; def II_TRUNC : InstrItinClass; +def II_WSBH : InstrItinClass; def II_XOR : InstrItinClass; def II_XORI : InstrItinClass; @@ -169,7 +207,7 @@ // Mips Generic instruction itineraries. //===----------------------------------------------------------------------===// def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ - InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>, + InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>, InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>, InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>, InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>, @@ -198,6 +236,8 @@ InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>, InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>, InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>, + InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>, + InstrItinData<II_INS , [InstrStage<1, [ALU]>]>, InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>, @@ -236,7 +276,29 @@ InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>, - InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>, + InstrItinData<II_B , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>, + InstrItinData<II_J , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>, + InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>, InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>, @@ -309,3 +371,5 @@ InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]> ]>; + +include "MipsScheduleP5600.td"