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diff llvm/docs/AMDGPU/gfx7_hwreg.rst @ 236:c4bab56944e8 llvm-original

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LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 79ff65ed7e25
children 1f2b6ac9f198
line wrap: on
line diff
--- a/llvm/docs/AMDGPU/gfx7_hwreg.rst	Wed Jul 21 10:27:27 2021 +0900
+++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst	Wed Nov 09 17:45:10 2022 +0900
@@ -5,10 +5,10 @@
     *                                                *
     **************************************************
 
-.. _amdgpu_synid7_hwreg:
+.. _amdgpu_synid_gfx7_hwreg:
 
 hwreg
-===========================
+=====
 
 Bits of a hardware register being accessed.
 
@@ -41,17 +41,17 @@
 
 Defined register *names* include:
 
-    =================== ==========================================
-    Name                Description
-    =================== ==========================================
-    HW_REG_MODE         Shader writeable mode bits.
-    HW_REG_STATUS       Shader read-only status.
-    HW_REG_TRAPSTS      Trap status.
-    HW_REG_HW_ID        Id of wave, simd, compute unit, etc.
-    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
-    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
-    HW_REG_IB_STS       Counters of outstanding instructions.
-    =================== ==========================================
+    ============================== ==========================================
+    Name                           Description
+    ============================== ==========================================
+    HW_REG_MODE                    Shader writeable mode bits.
+    HW_REG_STATUS                  Shader read-only status.
+    HW_REG_TRAPSTS                 Trap status.
+    HW_REG_HW_ID                   Id of wave, simd, compute unit, etc.
+    HW_REG_GPR_ALLOC               Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC               Per-wave LDS allocation.
+    HW_REG_IB_STS                  Counters of outstanding instructions.
+    ============================== ==========================================
 
 Examples: