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diff llvm/test/CodeGen/AMDGPU/vselect.ll @ 236:c4bab56944e8 llvm-original

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LLVM 16
author kono
date Wed, 09 Nov 2022 17:45:10 +0900
parents 79ff65ed7e25
children 1f2b6ac9f198
line wrap: on
line diff
--- a/llvm/test/CodeGen/AMDGPU/vselect.ll	Wed Jul 21 10:27:27 2021 +0900
+++ b/llvm/test/CodeGen/AMDGPU/vselect.ll	Wed Nov 09 17:45:10 2022 +0900
@@ -12,10 +12,10 @@
 ; VI: s_cmp_gt_i32
 ; VI: s_cselect_b32
 
-; SI: v_cmp_gt_i32_e32 vcc
-; SI: v_cndmask_b32_e32
-; SI: v_cmp_gt_i32_e32 vcc
-; SI: v_cndmask_b32_e32
+; SI-DAG: s_cmp_gt_i32
+; SI-DAG: s_cselect_b32
+; SI-DAG: s_cmp_gt_i32
+; SI-DAG: s_cselect_b32
 
 define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) {
 entry:
@@ -59,10 +59,10 @@
 ; VI: s_cselect_b32
 ; VI: s_cselect_b32
 
-; SI: v_cndmask_b32_e32
-; SI: v_cndmask_b32_e32
-; SI: v_cndmask_b32_e32
-; SI: v_cndmask_b32_e32
+; SI-DAG: s_cselect_b32
+; SI-DAG: s_cselect_b32
+; SI-DAG: s_cselect_b32
+; SI-DAG: s_cselect_b32
 
 define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) {
 entry: