--- a/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll	Wed Jul 21 10:27:27 2021 +0900
+++ b/llvm/test/Transforms/StructurizeCFG/one-loop-multiple-backedges.ll	Wed Nov 09 17:45:10 2022 +0900
@@ -1,43 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
 
 ; CHECK-NOT: br i1 true
 
 define void @blam(i32 addrspace(1)* nocapture %arg, float %arg1, float %arg2) {
-; CHECK: bb:
+; CHECK-LABEL: @blam(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[TMP:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ [[TMP2:%.*]], [[FLOW1:%.*]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = fcmp ult float [[ARG1:%.*]], 3.500000e+00
+; CHECK-NEXT:    [[TMP4_INV:%.*]] = xor i1 [[TMP4]], true
+; CHECK-NEXT:    br i1 [[TMP4_INV]], label [[BB5:%.*]], label [[FLOW:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[TMP6:%.*]] = fcmp uge float 0.000000e+00, [[ARG2:%.*]]
+; CHECK-NEXT:    br label [[FLOW]]
+; CHECK:       Flow:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i32 [ 15, [[BB5]] ], [ undef, [[BB3]] ]
+; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ [[TMP6]], [[BB5]] ], [ [[TMP4]], [[BB3]] ]
+; CHECK-NEXT:    br i1 [[TMP1]], label [[BB7:%.*]], label [[FLOW1]]
+; CHECK:       bb7:
+; CHECK-NEXT:    [[TMP8:%.*]] = add nuw nsw i64 [[TMP]], 1
+; CHECK-NEXT:    [[TMP9:%.*]] = icmp sge i64 [[TMP8]], 5
+; CHECK-NEXT:    br label [[FLOW1]]
+; CHECK:       Flow1:
+; CHECK-NEXT:    [[TMP2]] = phi i64 [ [[TMP8]], [[BB7]] ], [ undef, [[FLOW]] ]
+; CHECK-NEXT:    [[TMP3:%.*]] = phi i32 [ 255, [[BB7]] ], [ [[TMP0]], [[FLOW]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = phi i1 [ [[TMP9]], [[BB7]] ], [ true, [[FLOW]] ]
+; CHECK-NEXT:    br i1 [[TMP4]], label [[BB10:%.*]], label [[BB3]]
+; CHECK:       bb10:
+; CHECK-NEXT:    store i32 [[TMP3]], i32 addrspace(1)* [[ARG:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
 bb:
   br label %bb3
 
-; CHECK: bb3:
-; CHECK:   %tmp4.inv = xor i1 %tmp4, true
-; CHECK:   br i1 %tmp4.inv, label %bb5, label %Flow
 bb3:                                              ; preds = %bb7, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb7 ]
   %tmp4 = fcmp ult float %arg1, 3.500000e+00
   br i1 %tmp4, label %bb7, label %bb5
 
-; CHECK: bb5:
-; CHECK:   %tmp6.inv = xor i1 %tmp6, true
-; CHECK:   br label %Flow
 bb5:                                              ; preds = %bb3
   %tmp6 = fcmp olt float 0.000000e+00, %arg2
   br i1 %tmp6, label %bb10, label %bb7
 
-; CHECK: Flow:
-; CHECK:   %0 = phi i1 [ %tmp6.inv, %bb5 ], [ %tmp4, %bb3 ]
-; CHECK:   br i1 %0, label %bb7, label %Flow1
 
-; CHECK: bb7:
-; CHECK:   br label %Flow1
 bb7:                                              ; preds = %bb5, %bb3
   %tmp8 = add nuw nsw i64 %tmp, 1
   %tmp9 = icmp slt i64 %tmp8, 5
   br i1 %tmp9, label %bb3, label %bb10
 
-; CHECK: Flow1:
-; CHECK:   %3 = phi i1 [ %tmp9.inv, %bb7 ], [ true, %Flow ]
-; CHECK:   br i1 %3, label %bb10, label %bb3
 
-; CHECK: bb10:
 bb10:                                             ; preds = %bb7, %bb5
   %tmp11 = phi i32 [ 15, %bb5 ], [ 255, %bb7 ]
   store i32 %tmp11, i32 addrspace(1)* %arg, align 4