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view llvm/test/TableGen/cond-empty-list-arg.td @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
parents
children 2e18cbf3894f
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// RUN: llvm-tblgen %s
// XFAIL: vg_leak

class C<bit cond> {
  bit true = 1;
  list<int> X = !cond(cond: [1, 2, 3], true : []);
  list<int> Y = !cond(cond: [], true : [4, 5, 6]);
}