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view llvm/test/TableGen/dag-isel-subregs.td @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
parents
children 2e18cbf3894f
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// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s

include "reg-with-subregs-common.td"

// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::EXTRACT_SUBVECTOR),
// CHECK: OPC_CheckChild1Integer, 0,
// CHECK: OPC_EmitInteger, MVT::i32, sub0_sub1,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
          (EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;

// CHECK: OPC_CheckChild1Integer, 15,
// CHECK: OPC_EmitInteger, MVT::i32, 5|128,1/*133*/,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
          (EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;