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view test/CodeGen/AMDGPU/input-mods.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 1172e4bd9c6f
children
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG
;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM

;EG-LABEL: {{^}}test:
;EG: EXP_IEEE *
;CM-LABEL: {{^}}test:
;CM: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X|
;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X|
;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X|
;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X|

define amdgpu_ps void @test(<4 x float> inreg %reg0) {
   %r0 = extractelement <4 x float> %reg0, i32 0
   %r1 = call float @llvm.fabs.f32(float %r0)
   %r2 = fsub float -0.000000e+00, %r1
   %r3 = call float @llvm.exp2.f32(float %r2)
   %vec = insertelement <4 x float> undef, float %r3, i32 0
   call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
   ret void
}

declare float @llvm.exp2.f32(float) readnone
declare float @llvm.fabs.f32(float) readnone
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)