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view test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 60c9769439b8
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; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
; rdar://11331541

define i32 @t(i32 %a) nounwind {
; CHECK-LABEL: t:
; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
; CHECK: eors [[REG2]], [[REG1]]
  %tmp0 = ashr i32 %a, 31
  %tmp1 = xor i32 %tmp0, %a
  ret i32 %tmp1
}