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view test/MC/Mips/mips32r6/invalid.s @ 85:5e5d649e25d2

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Update LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Thu, 19 Feb 2015 15:19:25 +0900
parents 54457678186b
children afa8332a0e37
line wrap: on
line source

# Instructions that are available for the current ISA but should be rejected by
# the assembler (e.g. invalid set of operands or operand's restrictions not met).

# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
# RUN: FileCheck %s < %t1 -check-prefix=ASM

        .text
        .set noreorder
        .set noat
        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
        ldc2    $8,-21181($at)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
        sdc2    $20,23157($s2)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
        swc2    $25,24880($s0)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled