view llvm/test/CodeGen/AMDGPU/andorxorinvimm.ll @ 223:5f17cb93ff66 llvm-original

LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
parents 1d019706d866
children 1f2b6ac9f198
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; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s

; SI-LABEL: {{^}}s_or_to_orn2:
; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_or_to_orn2(i32 addrspace(1)* %out, i32 %in) {
  %x = or i32 %in, -51
  store i32 %x, i32 addrspace(1)* %out
  ret void
}

; SI-LABEL: {{^}}s_or_to_orn2_imm0:
; SI: s_orn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_or_to_orn2_imm0(i32 addrspace(1)* %out, i32 %in) {
  %x = or i32 -51, %in
  store i32 %x, i32 addrspace(1)* %out
  ret void
}

; SI-LABEL: {{^}}s_and_to_andn2:
; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_and_to_andn2(i32 addrspace(1)* %out, i32 %in) {
  %x = and i32 %in, -51
  store i32 %x, i32 addrspace(1)* %out
  ret void
}

; SI-LABEL: {{^}}s_and_to_andn2_imm0:
; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_and_to_andn2_imm0(i32 addrspace(1)* %out, i32 %in) {
  %x = and i32 -51, %in
  store i32 %x, i32 addrspace(1)* %out
  ret void
}

; SI-LABEL: {{^}}s_xor_to_xnor:
; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_xor_to_xnor(i32 addrspace(1)* %out, i32 %in) {
  %x = xor i32 %in, -51
  store i32 %x, i32 addrspace(1)* %out
  ret void
}

; SI-LABEL: {{^}}s_xor_to_xnor_imm0:
; SI: s_xnor_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
define amdgpu_kernel void @s_xor_to_xnor_imm0(i32 addrspace(1)* %out, i32 %in) {
  %x = xor i32 -51, %in
  store i32 %x, i32 addrspace(1)* %out
  ret void
}