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view llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir @ 223:5f17cb93ff66 llvm-original
LLVM13 (2021/7/18)
author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
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date | Sun, 18 Jul 2021 22:43:00 +0900 |
parents | 79ff65ed7e25 |
children |
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=post-RA-sched -o - %s 2>&1 | FileCheck %s # REQUIRES: asserts # CHECK-NOT: Stall in cycle --- name: hazard_rec_reset tracksRegLiveness: true body: | bb.0: successors: %bb.1 $m0 = S_MOV_B32 0 bb.1: liveins: $vgpr4 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec S_ENDPGM 0 ...