view llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @ 223:5f17cb93ff66 llvm-original

LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
parents 79ff65ed7e25
children 1f2b6ac9f198
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; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after finalize-isel | FileCheck %s
; This test verifies that the instruction selection will add the implicit
; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_CO_U32_e32.

; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_CO_U32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def $vcc, implicit $exec

define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
  %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
  %a = load volatile i32, i32 addrspace(1)* %in
  %b = load volatile i32, i32 addrspace(1)* %b_ptr
  %result = add i32 %a, %b
  store i32 %result, i32 addrspace(1)* %out
  ret void
}