view test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll @ 95:afa8332a0e37 LLVM3.8

LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/trunc-vector-store-assertion-failure.ll@60c9769439b8
children 803732b1fca8
line wrap: on
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s

; This tests for a bug in the SelectionDAG where custom lowered truncated
; vector stores at the end of a basic block were not being added to the
; LegalizedNodes list, which triggered an assertion failure.

; CHECK-LABEL: {{^}}test:
; CHECK: MEM_RAT_CACHELESS STORE_RAW
define void @test(<4 x i8> addrspace(1)* %out, i32 %cond, <4 x i8> %in) {
entry:
  %0 = icmp eq i32 %cond, 0
  br i1 %0, label %if, label %done

if:
  store <4 x i8> %in, <4 x i8> addrspace(1)* %out
  br label %done

done:
  ret void
}