Mercurial > hg > CbC > CbC_llvm
view llvm/test/CodeGen/AMDGPU/xor_add.ll @ 206:f17a3b42b08b
Added tag before-12 for changeset b7591485f4cd
author | Shinji KONO <kono@ie.u-ryukyu.ac.jp> |
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date | Mon, 07 Jun 2021 21:25:57 +0900 |
parents | 1d019706d866 |
children | 2e18cbf3894f |
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s ; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s ; =================================================================================== ; V_XAD_U32 ; =================================================================================== define amdgpu_ps float @xor_add(i32 %a, i32 %b, i32 %c) { ; VI-LABEL: xor_add: ; VI: ; %bb.0: ; VI-NEXT: v_xor_b32_e32 v0, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; VI-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: xor_add: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: xor_add: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float ret float %bc } ; ThreeOp instruction variant not used due to Constant Bus Limitations define amdgpu_ps float @xor_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) { ; VI-LABEL: xor_add_vgpr_a: ; VI: ; %bb.0: ; VI-NEXT: v_xor_b32_e32 v0, s2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v0 ; VI-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: xor_add_vgpr_a: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: xor_add_vgpr_a: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, s2, s3 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float ret float %bc } define amdgpu_ps float @xor_add_vgpr_all(i32 %a, i32 %b, i32 %c) { ; VI-LABEL: xor_add_vgpr_all: ; VI: ; %bb.0: ; VI-NEXT: v_xor_b32_e32 v0, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; VI-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: xor_add_vgpr_all: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: xor_add_vgpr_all: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float ret float %bc } define amdgpu_ps float @xor_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) { ; VI-LABEL: xor_add_vgpr_ab: ; VI: ; %bb.0: ; VI-NEXT: v_xor_b32_e32 v0, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; VI-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: xor_add_vgpr_ab: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, v1, s2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: xor_add_vgpr_ab: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, v1, s2 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float ret float %bc } define amdgpu_ps float @xor_add_vgpr_const(i32 %a, i32 %b) { ; VI-LABEL: xor_add_vgpr_const: ; VI: ; %bb.0: ; VI-NEXT: v_xor_b32_e32 v0, 3, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; VI-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: xor_add_vgpr_const: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_xad_u32 v0, v0, 3, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: xor_add_vgpr_const: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, 3, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; return to shader part epilog %x = xor i32 %a, 3 %result = add i32 %x, %b %bc = bitcast i32 %result to float ret float %bc }