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1 // The ARM UART, a memory mapped device
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2 #include "types.h"
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3 #include "defs.h"
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4 #include "param.h"
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5 #include "arm.h"
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6 #include "proc.h"
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7
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8 // trap routine
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9 void swi_handler (struct trapframe *r)
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10 {
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11 if (proc->killed)
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12 exit();
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13 proc->tf = r;
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14 syscall ();
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15 if (proc->killed)
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16 exit();
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17 }
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18
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19 // trap routine
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20 void irq_handler (struct trapframe *r)
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21 {
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22 // proc points to the current process. If the kernel is
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23 // running scheduler, proc is NULL.
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24 if (proc != NULL) {
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25 proc->tf = r;
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26 }
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27
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28 pic_dispatch (r);
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29 }
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30
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31 // trap routine
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32 void reset_handler (struct trapframe *r)
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33 {
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34 cli();
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35 cprintf ("reset at: 0x%x \n", r->pc);
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36 }
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37
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38 // trap routine
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39 void und_handler (struct trapframe *r)
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40 {
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41 cli();
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42 cprintf ("und at: 0x%x \n", r->pc);
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43 }
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44
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45 // trap routine
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46 void dabort_handler (struct trapframe *r)
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47 {
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48 uint dfs, fa;
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49
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50 cli();
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51
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52 // read data fault status register
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53 asm("MRC p15, 0, %[r], c5, c0, 0": [r]"=r" (dfs)::);
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54
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55 // read the fault address register
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56 asm("MRC p15, 0, %[r], c6, c0, 0": [r]"=r" (fa)::);
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57
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58 cprintf ("data abort: instruction 0x%x, fault addr 0x%x, reason 0x%x \n",
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59 r->pc, fa, dfs);
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60
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61 dump_trapframe (r);
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62 }
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63
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64 // trap routine
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65 void iabort_handler (struct trapframe *r)
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66 {
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67 uint ifs;
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68
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69 // read fault status register
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70 asm("MRC p15, 0, %[r], c5, c0, 0": [r]"=r" (ifs)::);
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71
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72 cli();
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73 cprintf ("prefetch abort at: 0x%x (reason: 0x%x)\n", r->pc, ifs);
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74 dump_trapframe (r);
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75 }
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76
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77 // trap routine
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78 void na_handler (struct trapframe *r)
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79 {
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80 cli();
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81 cprintf ("n/a at: 0x%x \n", r->pc);
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82 }
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83
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84 // trap routine
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85 void fiq_handler (struct trapframe *r)
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86 {
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87 cli();
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88 cprintf ("fiq at: 0x%x \n", r->pc);
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89 }
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90
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91 // low-level init code: in real hardware, lower memory is usually mapped
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92 // to flash during startup, we need to remap it to SDRAM
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93 void trap_init ( )
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94 {
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95 volatile uint32 *ram_start;
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96 char *stk;
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97 int i;
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98 uint modes[] = {FIQ_MODE, IRQ_MODE, ABT_MODE, UND_MODE};
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99
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100 // the opcode of PC relative load (to PC) instruction LDR pc, [pc,...]
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101 static uint32 const LDR_PCPC = 0xE59FF000U;
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102
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103 // create the excpetion vectors
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104 ram_start = (uint32*)VEC_TBL;
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105
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106 ram_start[0] = LDR_PCPC | 0x18; // Reset (SVC)
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107 ram_start[1] = LDR_PCPC | 0x18; // Undefine Instruction (UND)
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108 ram_start[2] = LDR_PCPC | 0x18; // Software interrupt (SVC)
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109 ram_start[3] = LDR_PCPC | 0x18; // Prefetch abort (ABT)
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110 ram_start[4] = LDR_PCPC | 0x18; // Data abort (ABT)
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111 ram_start[5] = LDR_PCPC | 0x18; // Not assigned (-)
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112 ram_start[6] = LDR_PCPC | 0x18; // IRQ (IRQ)
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113 ram_start[7] = LDR_PCPC | 0x18; // FIQ (FIQ)
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114
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115 ram_start[8] = (uint32)trap_reset;
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116 ram_start[9] = (uint32)trap_und;
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117 ram_start[10] = (uint32)trap_swi;
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118 ram_start[11] = (uint32)trap_iabort;
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119 ram_start[12] = (uint32)trap_dabort;
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120 ram_start[13] = (uint32)trap_na;
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121 ram_start[14] = (uint32)trap_irq;
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122 ram_start[15] = (uint32)trap_fiq;
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123
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124 // initialize the stacks for different mode
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125 for (i = 0; i < sizeof(modes)/sizeof(uint); i++) {
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126 stk = alloc_page ();
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127
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128 if (stk == NULL) {
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129 panic("failed to alloc memory for irq stack");
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130 }
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131
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132 set_stk (modes[i], (uint)stk);
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133 }
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134 }
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135
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136 void dump_trapframe (struct trapframe *tf)
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137 {
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138 cprintf ("r14_svc: 0x%x\n", tf->r14_svc);
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139 cprintf (" spsr: 0x%x\n", tf->spsr);
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140 cprintf (" r0: 0x%x\n", tf->r0);
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141 cprintf (" r1: 0x%x\n", tf->r1);
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142 cprintf (" r2: 0x%x\n", tf->r2);
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143 cprintf (" r3: 0x%x\n", tf->r3);
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144 cprintf (" r4: 0x%x\n", tf->r4);
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145 cprintf (" r5: 0x%x\n", tf->r5);
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146 cprintf (" r6: 0x%x\n", tf->r6);
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147 cprintf (" r7: 0x%x\n", tf->r7);
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148 cprintf (" r8: 0x%x\n", tf->r8);
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149 cprintf (" r9: 0x%x\n", tf->r9);
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150 cprintf (" r10: 0x%x\n", tf->r10);
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151 cprintf (" r11: 0x%x\n", tf->r11);
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152 cprintf (" r12: 0x%x\n", tf->r12);
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153 cprintf (" pc: 0x%x\n", tf->pc);
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154 }
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6
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155 void raise()
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156 {}
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