Mercurial > hg > CbC > CbC_xv6

comparison src/trap.cbc @ 367:650fac123133

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author anatofuz
date Fri, 03 Jul 2020 21:21:38 +0900
parents src/trap.c@3d7e1c9a852e
children dd720f057eb3
comparison
equal deleted inserted replaced
366:dcf47cf23ecc 367:650fac123133
1 // The ARM UART, a memory mapped device
2 #include "types.h"
3 #include "defs.h"
4 #include "param.h"
5 #include "arm.h"
6 #include "proc.h"
7
8
9 #include "kernel.h"
10
11 #define __ncode __code
12
13 extern __code exit(void);
14
15
16 __ncode cbc_swi_handler(struct trapframe* r) {
17 struct Context* kernel = &kernel_context->context;
18 struct Syscall* syscall = Gearef(kernel, Syscall)->syscall;
19
20 if (proc->killed) {
21 struct KernelRet* kernelret = Gearef(kernel, KernelRet)->kernel_ret;
22 goto meta(kernel, kernelret->exit);
23 }
24 proc->tf = r;
25 goto meta(kernel, syscall->dispatch);
26 }
27
28 // trap routine
29 void swi_handler (struct trapframe *r)
30 {
31 if (proc->killed)
32 exit();
33 proc->tf = r;
34 syscall ();
35 if (proc->killed)
36 exit();
37 }
38
39 // trap routine
40 void irq_handler (struct trapframe *r)
41 {
42 // proc points to the current process. If the kernel is
43 // running scheduler, proc is NULL.
44 if (proc != NULL) {
45 proc->tf = r;
46 }
47
48 pic_dispatch (r);
49 }
50
51 // trap routine
52 void reset_handler (struct trapframe *r)
53 {
54 cli();
55 cprintf ("reset at: 0x%x \n", r->pc);
56 }
57
58 // trap routine
59 void und_handler (struct trapframe *r)
60 {
61 cli();
62 cprintf ("und at: 0x%x \n", r->pc);
63 }
64
65 // trap routine
66 void dabort_handler (struct trapframe *r)
67 {
68 uint dfs, fa;
69
70 cli();
71
72 // read data fault status register
73 asm("MRC p15, 0, %[r], c5, c0, 0": [r]"=r" (dfs)::);
74
75 // read the fault address register
76 asm("MRC p15, 0, %[r], c6, c0, 0": [r]"=r" (fa)::);
77
78 cprintf ("data abort: instruction 0x%x, fault addr 0x%x, reason 0x%x \n",
79 r->pc, fa, dfs);
80
81 dump_trapframe (r);
82 }
83
84 // trap routine
85 void iabort_handler (struct trapframe *r)
86 {
87 uint ifs;
88
89 // read fault status register
90 asm("MRC p15, 0, %[r], c5, c0, 0": [r]"=r" (ifs)::);
91
92 cli();
93 cprintf ("prefetch abort at: 0x%x (reason: 0x%x)\n", r->pc, ifs);
94 dump_trapframe (r);
95 }
96
97 // trap routine
98 void na_handler (struct trapframe *r)
99 {
100 cli();
101 cprintf ("n/a at: 0x%x \n", r->pc);
102 }
103
104 // trap routine
105 void fiq_handler (struct trapframe *r)
106 {
107 cli();
108 cprintf ("fiq at: 0x%x \n", r->pc);
109 }
110
111 // low-level init code: in real hardware, lower memory is usually mapped
112 // to flash during startup, we need to remap it to SDRAM
113 void trap_init ( )
114 {
115 volatile uint32 *ram_start;
116 char *stk;
117 int i;
118 uint modes[] = {FIQ_MODE, IRQ_MODE, ABT_MODE, UND_MODE};
119
120 // the opcode of PC relative load (to PC) instruction LDR pc, [pc,...]
121 static uint32 const LDR_PCPC = 0xE59FF000U;
122
123 // create the excpetion vectors
124 ram_start = (uint32*)VEC_TBL;
125
126 ram_start[0] = LDR_PCPC | 0x18; // Reset (SVC)
127 ram_start[1] = LDR_PCPC | 0x18; // Undefine Instruction (UND)
128 ram_start[2] = LDR_PCPC | 0x18; // Software interrupt (SVC)
129 ram_start[3] = LDR_PCPC | 0x18; // Prefetch abort (ABT)
130 ram_start[4] = LDR_PCPC | 0x18; // Data abort (ABT)
131 ram_start[5] = LDR_PCPC | 0x18; // Not assigned (-)
132 ram_start[6] = LDR_PCPC | 0x18; // IRQ (IRQ)
133 ram_start[7] = LDR_PCPC | 0x18; // FIQ (FIQ)
134
135 ram_start[8] = (uint32)trap_reset;
136 ram_start[9] = (uint32)trap_und;
137 ram_start[10] = (uint32)trap_swi;
138 ram_start[11] = (uint32)trap_iabort;
139 ram_start[12] = (uint32)trap_dabort;
140 ram_start[13] = (uint32)trap_na;
141 ram_start[14] = (uint32)trap_irq;
142 ram_start[15] = (uint32)trap_fiq;
143
144 // initialize the stacks for different mode
145 for (i = 0; i < sizeof(modes)/sizeof(uint); i++) {
146 stk = alloc_page ();
147
148 if (stk == NULL) {
149 panic("failed to alloc memory for irq stack");
150 }
151
152 set_stk (modes[i], (uint)stk);
153 }
154 }
155
156 void dump_trapframe (struct trapframe *tf)
157 {
158 cprintf ("r14_svc: 0x%x\n", tf->r14_svc);
159 cprintf (" spsr: 0x%x\n", tf->spsr);
160 cprintf (" r0: 0x%x\n", tf->r0);
161 cprintf (" r1: 0x%x\n", tf->r1);
162 cprintf (" r2: 0x%x\n", tf->r2);
163 cprintf (" r3: 0x%x\n", tf->r3);
164 cprintf (" r4: 0x%x\n", tf->r4);
165 cprintf (" r5: 0x%x\n", tf->r5);
166 cprintf (" r6: 0x%x\n", tf->r6);
167 cprintf (" r7: 0x%x\n", tf->r7);
168 cprintf (" r8: 0x%x\n", tf->r8);
169 cprintf (" r9: 0x%x\n", tf->r9);
170 cprintf (" r10: 0x%x\n", tf->r10);
171 cprintf (" r11: 0x%x\n", tf->r11);
172 cprintf (" r12: 0x%x\n", tf->r12);
173 cprintf (" pc: 0x%x\n", tf->pc);
174 }
175 void raise()
176 {}